Revert "drm/i915/tgl: Add extra hdc flush workaround"

This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4.

The commit takes care Wa_1604544889 which was fixed on a0 stepping based on
a0 replan. So no SW workaround is required on any stepping now.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add extra hdc flush workaround")
Link: https://patchwork.freedesktop.org/patch/msgid/1c751032ce79c80c5485cae315f1a9904ce07cac.1583359940.git.caz.yokoyama@intel.com
(cherry picked from commit 175c4d9b3b9a60b4ea0b8cd034011808c6a03b05)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5e8928e..31455ec 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4000,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
 
                *cs++ = preparser_disable(false);
                intel_ring_advance(request, cs);
-
-               /*
-                * Wa_1604544889:tgl
-                */
-               if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
-                       flags = 0;
-                       flags |= PIPE_CONTROL_CS_STALL;
-                       flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
-
-                       flags |= PIPE_CONTROL_STORE_DATA_INDEX;
-                       flags |= PIPE_CONTROL_QW_WRITE;
-
-                       cs = intel_ring_begin(request, 6);
-                       if (IS_ERR(cs))
-                               return PTR_ERR(cs);
-
-                       cs = gen8_emit_pipe_control(cs, flags,
-                                                   LRC_PPHWSP_SCRATCH_ADDR);
-                       intel_ring_advance(request, cs);
-               }
        }
 
        return 0;