bfd/

	* elf32-spu.c (spu_elf_auto_overlay): Insert icache linker script
	after .toe instead of before .text section.  Set the LMA of all
	overlay sections to their icache IA address.
	(spu_elf_find_overlays): Determine icache set id without reference
	to the LMA.

ld/testsuite/
	* ld-spu/icache1.d: Update to new section layout.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 140823f..393a8e2 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2009-10-01  Ulrich Weigand  <uweigand@de.ibm.com>
+
+       * elf32-spu.c (spu_elf_auto_overlay): Insert icache linker script
+       after .toe instead of before .text section.  Set the LMA of all
+       overlay sections to their icache IA address.
+       (spu_elf_find_overlays): Determine icache set id without reference
+       to the LMA.
+
 2009-09-30  Tristan Gingold  <gingold@adacore.com>
 
        * configure.com: Use hosts/alphavms.h on both alpha and ia64 VMS.

diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c
index 13d3a53..890f260 100644 (file)
--- a/bfd/elf32-spu.c
+++ b/bfd/elf32-spu.c
@@ -678,9 +678,10 @@ spu_elf_find_overlays (struct bfd_link_info *info)
   ovl_end = alloc_sec[0]->vma + alloc_sec[0]->size;
   if (htab->params->ovly_flavour == ovly_soft_icache)
     {
+      unsigned int prev_buf = 0, set_id = 0;
+
       /* Look for an overlapping vma to find the first overlay section.  */
       bfd_vma vma_start = 0;
-      bfd_vma lma_start = 0;
 
       for (i = 1; i < n; i++)
        {
@@ -689,10 +690,6 @@ spu_elf_find_overlays (struct bfd_link_info *info)
            {
              asection *s0 = alloc_sec[i - 1];
              vma_start = s0->vma;
-             if (strncmp (s0->name, ".ovl.init", 9) != 0)
-               lma_start = s0->lma;
-             else
-               lma_start = s->lma;
              ovl_end = (s0->vma
                         + ((bfd_vma) 1
                            << (htab->num_lines_log2 + htab->line_size_log2)));
@@ -717,8 +714,10 @@ spu_elf_find_overlays (struct bfd_link_info *info)
          if (strncmp (s->name, ".ovl.init", 9) != 0)
            {
              num_buf = ((s->vma - vma_start) >> htab->line_size_log2) + 1;
-             if (((s->vma - vma_start) & (htab->params->line_size - 1))
-                 || ((s->lma - lma_start) & (htab->params->line_size - 1)))
+             set_id = (num_buf == prev_buf)? set_id + 1 : 0;
+             prev_buf = num_buf;
+
+             if ((s->vma - vma_start) & (htab->params->line_size - 1))
                {
                  info->callbacks->einfo (_("%X%P: overlay section %A "
                                            "does not start on a cache line.\n"),
@@ -737,7 +736,7 @@ spu_elf_find_overlays (struct bfd_link_info *info)
 
              alloc_sec[ovl_index++] = s;
              spu_elf_section_data (s)->u.o.ovl_index
-               = ((s->lma - lma_start) >>  htab->line_size_log2) + 1;
+               = (set_id << htab->num_lines_log2) + num_buf;
              spu_elf_section_data (s)->u.o.ovl_buf = num_buf;
            }
        }
@@ -4531,13 +4530,12 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
 
   script = htab->params->spu_elf_open_overlay_script ();
 
-  if (fprintf (script, "SECTIONS\n{\n") <= 0)
-    goto file_err;
-
   if (htab->params->ovly_flavour == ovly_soft_icache)
     {
+      if (fprintf (script, "SECTIONS\n{\n") <= 0)
+       goto file_err;
+
       if (fprintf (script,
-                  " .data.icache ALIGN (16) : { *(.ovtab) *(.data.icache) }\n"
                   " . = ALIGN (%u);\n"
                   " .ovl.init : { *(.ovl.init) }\n"
                   " . = ABSOLUTE (ADDR (.ovl.init));\n",
@@ -4552,10 +4550,10 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
          unsigned int vma, lma;
 
          vma = (indx & (htab->params->num_lines - 1)) << htab->line_size_log2;
-         lma = indx << htab->line_size_log2;
+         lma = vma + (((indx >> htab->num_lines_log2) + 1) << 18);
 
          if (fprintf (script, " .ovly%u ABSOLUTE (ADDR (.ovl.init)) + %u "
-                      ": AT (ALIGN (LOADADDR (.ovl.init) + SIZEOF (.ovl.init), 16) + %u) {\n",
+                              ": AT (LOADADDR (.ovl.init) + %u) {\n",
                       ovlynum, vma, lma) <= 0)
            goto file_err;
 
@@ -4573,9 +4571,15 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
       if (fprintf (script, " . = ABSOLUTE (ADDR (.ovl.init)) + %u;\n",
                   1 << (htab->num_lines_log2 + htab->line_size_log2)) <= 0)
        goto file_err;
+
+      if (fprintf (script, "}\nINSERT AFTER .toe;\n") <= 0)
+       goto file_err;
     }
   else
     {
+      if (fprintf (script, "SECTIONS\n{\n") <= 0)
+       goto file_err;
+
       if (fprintf (script,
                   " . = ALIGN (16);\n"
                   " .ovl.init : { *(.ovl.init) }\n"
@@ -4627,13 +4631,13 @@ spu_elf_auto_overlay (struct bfd_link_info *info)
            goto file_err;
        }
 
+      if (fprintf (script, "}\nINSERT BEFORE .text;\n") <= 0)
+       goto file_err;
     }
 
   free (ovly_map);
   free (ovly_sections);
 
-  if (fprintf (script, "}\nINSERT BEFORE .text;\n") <= 0)
-    goto file_err;
   if (fclose (script) != 0)
     goto file_err;
 

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index ec944b6..fa8ec9e 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2009-10-01  Ulrich Weigand  <uweigand@de.ibm.com>
+
+       * ld-spu/icache1.d: Update to new section layout.
+
 2009-09-24  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/10630

diff --git a/ld/testsuite/ld-spu/icache1.d b/ld/testsuite/ld-spu/icache1.d
index f73c6c0..01b42ba 100644 (file)
--- a/ld/testsuite/ld-spu/icache1.d
+++ b/ld/testsuite/ld-spu/icache1.d
@@ -5,15 +5,51 @@
 .* elf32-spu
 
 
-Disassembly of section .ovl.init:
-00000000 <__icache_fileoff>:
+Disassembly of section \.text:
+
+00000000 <_start>:
+.*     41 00 02 03     ilhu    \$3,4
+.*     60 88 00 03     iohl    \$3,4096        # 1000
+.*     32 00 03 80     br      24.*
+0000000c <__icache_br_handler>:
+   c:  00 00 00 00     stop
+00000010 <__icache_call_handler>:
+       \.\.\.
+  20:  00 04 08 00.*
+  24:  31 00 02 4b     brasl   \$75,10 <__icache_call_handler>
+  28:  a0 00 00 08.*
+  2c:  00 00 fc 80.*
+       \.\.\.
+
+Disassembly of section \.data:
+
+.* <.data>:
+.*     00 04 08 00     .*
+.*     00 04 0d 04     .*
+.*     00 04 0c 00     .*
+.*     00 08 10 00     .*
+
+Disassembly of section \.bss:
+
+.* <__icache_tag_array>:
+       \.\.\.
+
+.* <__icache_rewrite_to>:
+       \.\.\.
+
+.* <__icache_rewrite_from>:
+       \.\.\.
+
+Disassembly of section \.ovl\.init:
+
+00000400 <__icache_fileoff>:
 .*     00 00 00 00.*
 .*     00 00 02 00.*
        \.\.\.
 
 Disassembly of section \.ovly1:
 
-00000000 <\.ovly1>:
+00000400 <\.ovly1>:
 .*     ai      \$1,\$1,64      # 40
 .*     lqd     \$0,16\(\$1\)
 .*     bi      \$0
@@ -21,36 +57,36 @@ Disassembly of section \.ovly1:
 
 Disassembly of section \.ovly2:
 
-00000400 <f1>:
+00000800 <f1>:
 .*     40 20 00 00     nop     \$0
 .*     24 00 40 80     stqd    \$0,16\(\$1\)
 .*     1c f0 00 81     ai      \$1,\$1,-64
 .*     24 00 00 81     stqd    \$1,0\(\$1\)
-.*     33 00 78 80     brsl    \$0,7d4 .*
-.*     33 00 7a 00     brsl    \$0,7e4 .*
-       \.\.\.
-.*     32 00 17 80     br      7f4 .*
-       \.\.\.
- 7d0:  00 04 09 04.*
- 7d4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 7d8:  a0 00 04 10.*
- 7dc:  00 00 e6 00.*
- 7e0:  00 04 08 00.*
- 7e4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 7e8:  a0 00 04 14.*
- 7ec:  00 00 07 80.*
- 7f0:  00 04 00 00.*
- 7f4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 7f8:  20 00 07 38.*
- 7fc:  00 7f 0e 80.*
+.*     33 00 78 80     brsl    \$0,bd4 .*
+.*     33 00 7a 00     brsl    \$0,be4 .*
+       \.\.\.
+.*     32 00 17 80     br      bf4 .*
+       \.\.\.
+ bd0:  00 04 0d 04.*
+ bd4:  31 00 01 cb     brasl   \$75,c .*
+ bd8:  a0 00 08 10.*
+ bdc:  00 00 e6 00.*
+ be0:  00 04 0c 00.*
+ be4:  31 00 01 cb     brasl   \$75,c .*
+ be8:  a0 00 08 14.*
+ bec:  00 00 07 80.*
+ bf0:  00 04 04 00.*
+ bf4:  31 00 01 cb     brasl   \$75,c .*
+ bf8:  20 00 0b 38.*
+ bfc:  00 7f 0e 80.*
 
 Disassembly of section \.ovly3:
 
-00000800 <f3>:
+00000c00 <f3>:
        \.\.\.
 .*     35 00 00 00     bi      \$0
 
-00000904 <f2>:
+00000d04 <f2>:
 .*     1c e0 00 81     ai      \$1,\$1,-128
 .*     24 00 00 81     stqd    \$1,0\(\$1\)
        \.\.\.
@@ -60,11 +96,11 @@ Disassembly of section \.ovly3:
 
 Disassembly of section \.ovly4:
 
-00000c00 <f5>:
+00001000 <f5>:
 .*     24 00 40 80     stqd    \$0,16\(\$1\)
 .*     24 f8 00 81     stqd    \$1,-512\(\$1\)
 .*     1c 80 00 81     ai      \$1,\$1,-512
-.*     33 7f fe 80     brsl    \$0,c00 <f5>    # c00
+.*     33 7f fe 80     brsl    \$0,1000 <f5>   # 1000
        \.\.\.
 .*     42 01 00 03     ila     \$3,200.*
 .*     18 00 c0 81     a       \$1,\$1,\$3
@@ -74,99 +110,84 @@ Disassembly of section \.ovly4:
 
 Disassembly of section \.ovly5:
 
-00000000 <\.ovly5>:
+00000400 <\.ovly5>:
        \.\.\.
 .*     42 01 00 03     ila     \$3,200 .*
 .*     18 00 c0 81     a       \$1,\$1,\$3
 .*     34 00 40 80     lqd     \$0,16\(\$1\)
-.*     30 00 7e 80     bra     3f4 .*
+.*     30 00 fe 80     bra     7f4 .*
        \.\.\.
- 3f0:  00 04 0c 00.*
- 3f4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 3f8:  a0 00 03 2c.*
- 3fc:  00 01 fe 80.*
+ 7f0:  00 04 10 00.*
+ 7f4:  31 00 01 cb     brasl   \$75,c .*
+ 7f8:  a0 00 07 2c.*
+ 7fc:  00 02 fe 80.*
 
 Disassembly of section \.ovly6:
 
-00000400 <\.ovly6>:
-.*     31 00 fa 80     brasl   \$0,7d4 .*
-.*     33 00 7c 00     brsl    \$0,7e4 .*
-       \.\.\.
-.*     32 00 19 80     br      7f4 .*
-       \.\.\.
- 7d0:  00 08 0c 00.*
- 7d4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 7d8:  a0 00 04 00.*
- 7dc:  00 01 7a 80.*
- 7e0:  00 08 0c 00.*
- 7e4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 7e8:  a0 00 04 04.*
- 7ec:  00 00 83 80.*
- 7f0:  00 08 00 00.*
- 7f4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- 7f8:  20 00 07 28.*
- 7fc:  00 7f 02 80.*
+00000800 <\.ovly6>:
+.*     31 01 7a 80     brasl   \$0,bd4 .*
+.*     33 00 7c 00     brsl    \$0,be4 .*
+       \.\.\.
+.*     32 00 19 80     br      bf4 .*
+       \.\.\.
+ bd0:  00 08 10 00.*
+ bd4:  31 00 01 cb     brasl   \$75,c .*
+ bd8:  a0 00 08 00.*
+ bdc:  00 03 7a 80.*
+ be0:  00 08 10 00.*
+ be4:  31 00 01 cb     brasl   \$75,c .*
+ be8:  a0 00 08 04.*
+ bec:  00 00 83 80.*
+ bf0:  00 08 04 00.*
+ bf4:  31 00 01 cb     brasl   \$75,c .*
+ bf8:  20 00 0b 28.*
+ bfc:  00 7f 02 80.*
 
 Disassembly of section \.ovly7:
 
-00000800 <\.ovly7>:
+00000c00 <\.ovly7>:
 .*     41 7f ff 83     ilhu    \$3,65535       # ffff
 .*     60 f8 30 03     iohl    \$3,61536       # f060
 .*     18 00 c0 84     a       \$4,\$1,\$3
 .*     00 20 00 00     lnop
 .*     04 00 02 01     ori     \$1,\$4,0
 .*     24 00 02 04     stqd    \$4,0\(\$4\)
-.*     33 00 77 80     brsl    \$0,bd4 .*
-.*     33 00 79 00     brsl    \$0,be4 .*
+.*     33 00 77 80     brsl    \$0,fd4 .*
+.*     33 00 79 00     brsl    \$0,fe4 .*
 .*     34 00 00 81     lqd     \$1,0\(\$1\)
        \.\.\.
-.*     32 00 16 00     br      bf4 .*
+.*     32 00 16 00     br      ff4 .*
        \.\.\.
- bd0:  00 04 0c 00.*
- bd4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- bd8:  a0 00 08 18.*
- bdc:  00 00 0a 80.*
- be0:  00 08 0c 00.*
- be4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- be8:  a0 00 08 1c.*
- bec:  00 00 05 80.*
- bf0:  00 08 04 00.*
- bf4:  31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
- bf8:  20 00 0b 44.*
- bfc:  00 7f 01 80.*
+     fd0:      00 04 10 00.*
+     fd4:      31 00 01 cb     brasl   \$75,c .*
+     fd8:      a0 00 0c 18.*
+     fdc:      00 00 0a 80.*
+     fe0:      00 08 10 00.*
+     fe4:      31 00 01 cb     brasl   \$75,c .*
+     fe8:      a0 00 0c 1c.*
+     fec:      00 00 05 80.*
+     ff0:      00 08 08 00.*
+     ff4:      31 00 01 cb     brasl   \$75,c .*
+     ff8:      20 00 0f 44.*
+     ffc:      00 7f 01 80.*
 
 Disassembly of section \.ovly8:
 
-00000c00 <f4>:
+00001000 <f4>:
 .*     24 00 40 80     stqd    \$0,16\(\$1\)
 .*     24 f8 00 81     stqd    \$1,-512\(\$1\)
 .*     1c 80 00 81     ai      \$1,\$1,-512
-.*     31 01 fc 80     brasl   \$0,fe4 .*
-       \.\.\.
-.*     32 00 18 80     br      ff4 .*
-       \.\.\.
-     fe0:      00 04 09 04.*
-     fe4:      31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
-     fe8:      a0 00 0c 0c.*
-     fec:      00 00 dc 00.*
-     ff0:      00 08 08 00.*
-     ff4:      31 02 01 cb     brasl   \$75,100c <__icache_br_handler>
-     ff8:      20 00 0f 30.*
-     ffc:      00 7f 02 80.*
-
-Disassembly of section \.text:
-
-00001000 <_start>:
-.*     41 00 02 03     ilhu    \$3,4
-.*     60 86 00 03     iohl    \$3,3072        # c00
-.*     32 00 03 80     br      1024.*
-0000100c <__icache_br_handler>:
-    100c:      00 00 00 00     stop
-00001010 <__icache_call_handler>:
-       \.\.\.
-    1020:      00 04 04 00.*
-    1024:      31 02 02 4b     brasl   \$75,1010 <__icache_call_handler>
-    1028:      a0 00 10 08.*
-    102c:      00 7e 7c 80.*
+.*     31 02 7c 80     brasl   \$0,13e4 .*
+       \.\.\.
+.*     32 00 18 80     br      13f4 .*
+       \.\.\.
+    13e0:      00 04 0d 04.*
+    13e4:      31 00 01 cb     brasl   \$75,c .*
+    13e8:      a0 00 10 0c.*
+    13ec:      00 03 dc 00.*
+    13f0:      00 08 0c 00.*
+    13f4:      31 00 01 cb     brasl   \$75,c .*
+    13f8:      20 00 13 30.*
+    13fc:      00 7f 02 80.*
 
 #pass