misched: Add computeInstrLatency to TargetSchedModel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/TargetSchedule.h b/include/llvm/CodeGen/TargetSchedule.h
index 6a5359d..3adbe7d 100644 (file)
--- a/include/llvm/CodeGen/TargetSchedule.h
+++ b/include/llvm/CodeGen/TargetSchedule.h
@@ -74,6 +74,14 @@ public:
                                  const MachineInstr *UseMI, unsigned UseOperIdx,
                                  bool FindMin) const;
 
+  /// \brief Compute the instruction latency based on the available machine
+  /// model.
+  ///
+  /// Compute and return the expected latency of this instruction independent of
+  /// a particular use. computeOperandLatency is the prefered API, but this is
+  /// occasionally useful to help estimate instruction cost.
+  unsigned computeInstrLatency(const MachineInstr *MI) const;
+
   /// \brief Identify the processor corresponding to the current subtarget.
   unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
 

diff --git a/lib/CodeGen/TargetSchedule.cpp b/lib/CodeGen/TargetSchedule.cpp
index 6e7cccc..cf9d059 100644 (file)
--- a/lib/CodeGen/TargetSchedule.cpp
+++ b/lib/CodeGen/TargetSchedule.cpp
@@ -146,6 +146,10 @@ unsigned TargetSchedModel::computeOperandLatency(
     unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
 
     // Expected latency is the max of the stage latency and itinerary props.
+    // Rather than directly querying InstrItins stage latency, we call a TII
+    // hook to allow subtargets to specialize latency. This hook is only
+    // applicable to the InstrItins model. InstrSchedModel should model all
+    // special cases without TII hooks.
     if (!FindMin)
       InstrLatency = std::max(InstrLatency,
                               TII->defaultDefLatency(&SchedModel, DefMI));
@@ -185,3 +189,23 @@ unsigned TargetSchedModel::computeOperandLatency(
 #endif
   return 1;
 }
+
+unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
+  if (hasInstrItineraries()) {
+    // For the itinerary model, fall back to the old subtarget hook.
+    return TII->getInstrLatency(&InstrItins, MI);
+  }
+  if (hasInstrSchedModel()) {
+    unsigned Latency = 0;
+    const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
+    for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
+         DefIdx != DefEnd; ++DefIdx) {
+      // Lookup the definition's write latency in SubtargetInfo.
+      const MCWriteLatencyEntry *WLEntry =
+        STI->getWriteLatencyEntry(SCDesc, DefIdx);
+      Latency = std::max(Latency, WLEntry->Cycles);
+    }
+    return Latency;
+  }
+  return TII->defaultDefLatency(&SchedModel, MI);
+}