but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
The Mips RDHWR (Read Hardware Register) instruction was not
tested for assembler or dissassembler consumption. This patch
adds that functionality.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685
91177308-0d34-0410-b5e6-
96231b3b80d8
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ if (isMips64())
+ return MatchOperand_NoMatch;
+
// if the first token is not '$' we have error
if (Parser.getTok().isNot(AsmToken::Dollar))
return MatchOperand_NoMatch;
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+
+ if (!isMips64())
+ return MatchOperand_NoMatch;
//if the first token is not '$' we have error
if (Parser.getTok().isNot(AsmToken::Dollar))
return MatchOperand_NoMatch;
MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S,
Parser.getTok().getLoc());
- op->setRegKind(MipsOperand::Kind_HWRegs);
+ op->setRegKind(MipsOperand::Kind_HW64Regs);
Operands.push_back(op);
Parser.Lex(); // Eat reg number
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst,
+ unsigned RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ //Currently only hardware register 29 is supported
+ if (RegNo != 29)
+ return MCDisassembler::Fail;
+ Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
let ParserMatchClass = HWRegsAsmOperand;
}
-def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
+def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
let ParserMatchClass = HW64RegsAsmOperand;
}
# CHECK: xori $9, $6, 17767
0x38 0xc9 0x45 0x67
+
+# CHECK: .set push
+# CHECK: .set mips32r2
+# CHECK: rdhwr $5, $29
+# CHECK: .set pop
+0x7c 0x05 0xe8 0x3b
# CHECK: xori $9, $6, 17767
0x67 0x45 0xc9 0x38
+
+# CHECK: .set push
+# CHECK: .set mips32r2
+# CHECK: rdhwr $5, $29
+# CHECK: .set pop
+0x3b 0xe8 0x05 0x7c
# CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00]
# CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00]
# CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01]
+# CHECK: .set push
+# CHECK: .set mips32r2
+# CHECK: rdhwr $5, $29
+# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
add $9,$6,$7
add $9,$6,17767
addu $9,$6,-15001
neg $6,$7
negu $6,$7
move $7,$8
+ rdhwr $5, $29
# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
# CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00]
# CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01]
+# CHECK: .set push
+# CHECK: .set mips32r2
+# CHECK: rdhwr $5, $29
+# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
+
dadd $9,$6,$7
dadd $9,$6,17767
daddu $9,$6,-15001
multu $3,$5
dsubu $4,$3,$5
move $7,$8
+ rdhwr $5, $29