return getFalse(ITy);
}
- // FIXME: Use m_APInt to allow vector splat matches.
- ConstantInt *CI1, *CI2;
- if (!match(Op0, m_ICmp(Pred0, m_Add(m_Value(V), m_ConstantInt(CI1)),
- m_ConstantInt(CI2))))
+ // (icmp (add V, C0), C1) & (icmp V, C0)
+ if (!match(Op0, m_ICmp(Pred0, m_Add(m_Value(V), m_APInt(C0)), m_APInt(C1))))
return nullptr;
- if (!match(Op1, m_ICmp(Pred1, m_Specific(V), m_Specific(CI1))))
+ if (!match(Op1, m_ICmp(Pred1, m_Specific(V), m_Value())))
return nullptr;
auto *AddInst = cast<BinaryOperator>(Op0->getOperand(0));
+ if (AddInst->getOperand(1) != Op1->getOperand(1))
+ return nullptr;
+
bool isNSW = AddInst->hasNoSignedWrap();
bool isNUW = AddInst->hasNoUnsignedWrap();
- const APInt &CI1V = CI1->getValue();
- const APInt &CI2V = CI2->getValue();
- const APInt Delta = CI2V - CI1V;
- if (CI1V.isStrictlyPositive()) {
+ const APInt Delta = *C1 - *C0;
+ if (C0->isStrictlyPositive()) {
if (Delta == 2) {
if (Pred0 == ICmpInst::ICMP_ULT && Pred1 == ICmpInst::ICMP_SGT)
return getFalse(ITy);
return getFalse(ITy);
}
}
- if (CI1V.getBoolValue() && isNUW) {
+ if (C0->getBoolValue() && isNUW) {
if (Delta == 2)
if (Pred0 == ICmpInst::ICMP_ULT && Pred1 == ICmpInst::ICMP_UGT)
return getFalse(ITy);
ret i1 %cmp
}
+define <2 x i1> @and_of_icmps0_vec(<2 x i32> %b) {
+; CHECK-LABEL: @and_of_icmps0_vec(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %1 = add <2 x i32> %b, <i32 2, i32 2>
+ %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
+ %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
+ %cmp = and <2 x i1> %2, %cmp3
+ ret <2 x i1> %cmp
+}
+
define i1 @and_of_icmps1(i32 %b) {
; CHECK-LABEL: @and_of_icmps1(
; CHECK-NEXT: ret i1 false
ret i1 %cmp
}
+define <2 x i1> @and_of_icmps1_vec(<2 x i32> %b) {
+; CHECK-LABEL: @and_of_icmps1_vec(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
+ %2 = icmp slt <2 x i32> %1, <i32 4, i32 4>
+ %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
+ %cmp = and <2 x i1> %2, %cmp3
+ ret <2 x i1> %cmp
+}
+
define i1 @and_of_icmps2(i32 %b) {
; CHECK-LABEL: @and_of_icmps2(
; CHECK-NEXT: ret i1 false
ret i1 %cmp
}
+define <2 x i1> @and_of_icmps2_vec(<2 x i32> %b) {
+; CHECK-LABEL: @and_of_icmps2_vec(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %1 = add <2 x i32> %b, <i32 2, i32 2>
+ %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
+ %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
+ %cmp = and <2 x i1> %2, %cmp3
+ ret <2 x i1> %cmp
+}
+
define i1 @and_of_icmps3(i32 %b) {
; CHECK-LABEL: @and_of_icmps3(
; CHECK-NEXT: ret i1 false
ret i1 %cmp
}
+define <2 x i1> @and_of_icmps3_vec(<2 x i32> %b) {
+; CHECK-LABEL: @and_of_icmps3_vec(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
+ %2 = icmp sle <2 x i32> %1, <i32 3, i32 3>
+ %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
+ %cmp = and <2 x i1> %2, %cmp3
+ ret <2 x i1> %cmp
+}
+
define i1 @and_of_icmps4(i32 %b) {
; CHECK-LABEL: @and_of_icmps4(
; CHECK-NEXT: ret i1 false
ret i1 %cmp
}
+define <2 x i1> @and_of_icmps4_vec(<2 x i32> %b) {
+; CHECK-LABEL: @and_of_icmps4_vec(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
+ %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
+ %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
+ %cmp = and <2 x i1> %2, %cmp3
+ ret <2 x i1> %cmp
+}
+
define i1 @and_of_icmps5(i32 %b) {
; CHECK-LABEL: @and_of_icmps5(
; CHECK-NEXT: ret i1 false
ret i1 %cmp
}
+define <2 x i1> @and_of_icmps5_vec(<2 x i32> %b) {
+; CHECK-LABEL: @and_of_icmps5_vec(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
+ %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
+ %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
+ %cmp = and <2 x i1> %2, %cmp3
+ ret <2 x i1> %cmp
+}
+
define i1 @or_of_icmps0(i32 %b) {
; CHECK-LABEL: @or_of_icmps0(
; CHECK-NEXT: ret i1 true