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PCI: designware: Fix comment for setting number of lanes
author
Mohit Kumar
<mohit.kumar@st.com>
Wed, 16 Apr 2014 16:23:28 +0000
(10:23 -0600)
committer
Bjorn Helgaas
<bhelgaas@google.com>
Wed, 16 Apr 2014 16:23:28 +0000
(10:23 -0600)
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
drivers/pci/host/pcie-designware.c
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diff --git
a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index
509a29d
..
8909e77
100644
(file)
--- a/
drivers/pci/host/pcie-designware.c
+++ b/
drivers/pci/host/pcie-designware.c
@@
-764,7
+764,7
@@
void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
- /* set the number of l
ines as 4
*/
+ /* set the number of l
anes
*/
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {