ASoC: wcd934x: fix default value for FLL threshold

The default value of CPE FLL threshold register needs to be updated
to 0x20 as per the hardware specification. Change fixes this by
adding this register to the codec register defaults.

CRs-Fixed: 1083199
Change-Id: Ib19d78f0834803c75b255ee3a119e043ffb8a988
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>

diff --git a/sound/soc/codecs/wcd934x/wcd934x.c b/sound/soc/codecs/wcd934x/wcd934x.c
index 30c23df..65386b1 100644 (file)
--- a/sound/soc/codecs/wcd934x/wcd934x.c
+++ b/sound/soc/codecs/wcd934x/wcd934x.c
@@ -8005,6 +8005,7 @@ static const struct tavil_reg_mask_val tavil_codec_reg_defaults[] = {
        {WCD934X_HPH_OCP_CTL, 0xFF, 0x3A}, /* OCP current limit */
        {WCD934X_HPH_L_TEST, 0x01, 0x01},
        {WCD934X_HPH_R_TEST, 0x01, 0x01},
+       {WCD934X_CPE_FLL_CONFIG_CTL_2, 0xFF, 0x20},
 };
 
 static const struct tavil_reg_mask_val tavil_codec_reg_init_1_1_val[] = {