#define RST_RESERVED_BITS GENMASK_ULL(31, 0)
/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
-#define INFO1_CLEAR 0
#define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
#define INFO1_DTRANEND1 BIT(20)
#define INFO1_DTRANEND1_OLD BIT(17)
renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
{
struct renesas_sdhi *priv = host_to_priv(host);
+ u32 dma_irqs = INFO1_DTRANEND0 |
+ (priv->quirks && priv->quirks->old_info1_layout ?
+ INFO1_DTRANEND1_OLD : INFO1_DTRANEND1);
if (!host->chan_tx || !host->chan_rx)
return;
- if (!enable)
- writel(INFO1_CLEAR, host->ctl + DM_CM_INFO1);
+ writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
if (priv->dma_priv.enable)
priv->dma_priv.enable(host, enable);
renesas_sdhi_internal_dmac_enable_dma(host, true);
}
+static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host)
+{
+ struct renesas_sdhi *priv = host_to_priv(host);
+ struct renesas_sdhi_dma *dma_priv = &priv->dma_priv;
+
+ u32 dma_irqs = INFO1_DTRANEND0 |
+ (priv->quirks && priv->quirks->old_info1_layout ?
+ INFO1_DTRANEND1_OLD : INFO1_DTRANEND1);
+ u32 status = readl(host->ctl + DM_CM_INFO1);
+
+ if (status & dma_irqs) {
+ writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1);
+ set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags);
+ if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags))
+ tasklet_schedule(&dma_priv->dma_complete);
+ }
+
+ return status & dma_irqs;
+}
+
static void
renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host)
{
struct renesas_sdhi *priv = host_to_priv(host);
+ struct renesas_sdhi_dma *dma_priv = &priv->dma_priv;
- tasklet_schedule(&priv->dma_priv.dma_complete);
+ set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags);
+ if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) ||
+ host->data->error)
+ tasklet_schedule(&dma_priv->dma_complete);
}
/*
dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
}
+ priv->dma_priv.end_flags = 0;
renesas_sdhi_internal_dmac_enable_dma(host, true);
/* set dma parameters */
static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
{
struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+ struct renesas_sdhi *priv = host_to_priv(host);
tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
- /* start the DMAC */
- writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL);
+ if (!host->cmd->error) {
+ /* start the DMAC */
+ writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL);
+ } else {
+ /* on CMD errors, simulate DMA end immediately */
+ set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags);
+ if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags))
+ tasklet_schedule(&priv->dma_priv.dma_complete);
+ }
}
static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
{
struct renesas_sdhi *priv = host_to_priv(host);
- /* Disable DMAC interrupts, we don't use them */
+ /* Disable DMAC interrupts initially */
writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK);
writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK);
+ writel(0, host->ctl + DM_CM_INFO1);
+ writel(0, host->ctl + DM_CM_INFO2);
/* Each value is set to non-zero to assume "enabling" each DMA */
host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
.abort = renesas_sdhi_internal_dmac_abort_dma,
.dataend = renesas_sdhi_internal_dmac_dataend_dma,
.end = renesas_sdhi_internal_dmac_end_dma,
+ .dma_irq = renesas_sdhi_internal_dmac_dma_irq,
};
static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)