/* seems to be defined on mingw-gcc */
#undef i386
+static CPU_RESET( CPU_MODEL );
+
int i386_parity_table[256];
MODRM_TABLE i386_MODRM_table[256];
-extern void i386_trap_with_error(i386_state* cpustate, int irq, int irq_gate, int trap_level, UINT32 err);
+static void i386_trap_with_error(i386_state* cpustate, int irq, int irq_gate, int trap_level, UINT32 err);
static void i286_task_switch(i386_state* cpustate, UINT16 selector, UINT8 nested);
static void i386_task_switch(i386_state* cpustate, UINT16 selector, UINT8 nested);
-//static void build_opcode_table(i386_state *cpustate, UINT32 features);
-//static void zero_state(i386_state *cpustate);
-
-extern void i386_op_decode_opcode_main(i386_state *cpustate);
-extern void i386_op_decode_two_byte_main(i386_state *cpustate);
-extern void i386_op_decode_three_byte38_main(i386_state *cpustate);
-extern void i386_op_decode_three_byte3a_main(i386_state *cpustate);
-extern void i386_op_decode_three_byte66_main(i386_state *cpustate);
-extern void i386_op_decode_three_bytef2_main(i386_state *cpustate);
-extern void i386_op_decode_three_bytef3_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte3866_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte38f2_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte38f3_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte3a66_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte3af2_main(i386_state *cpustate);
-
-extern void i386_pentium_smi_main(i386_state *cpustate);
+static void build_opcode_table(i386_state *cpustate, UINT32 features);
+static void zero_state(i386_state *cpustate);
static void pentium_smi(i386_state* cpustate);
#define FAULT(fault,error) {cpustate->ext = 1; i386_trap_with_error(cpustate,fault,0,0,error); return;}
/*************************************************************************/
-UINT32 i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *seg, UINT64 *desc )
+static UINT32 i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *seg, UINT64 *desc )
{
UINT32 v1,v2;
UINT32 base, limit;
return 1;
}
-void i386_load_call_gate(i386_state* cpustate, I386_CALL_GATE *gate)
+static void i386_load_call_gate(i386_state* cpustate, I386_CALL_GATE *gate)
{
UINT32 v1,v2;
UINT32 base,limit;
gate->dpl = (gate->ar >> 5) & 0x03;
}
-void i386_set_descriptor_accessed(i386_state *cpustate, UINT16 selector)
+static void i386_set_descriptor_accessed(i386_state *cpustate, UINT16 selector)
{
// assume the selector is valid, we don't need to check it again
UINT32 base, addr;
cpustate->program->write_data8(addr, rights | 1);
}
-void i386_load_segment_descriptor(i386_state *cpustate, int segment )
+static void i386_load_segment_descriptor(i386_state *cpustate, int segment )
{
if (PROTECTED_MODE)
{
}
/* Retrieves the stack selector located in the current TSS */
-UINT32 i386_get_stack_segment(i386_state* cpustate, UINT8 privilege)
+static UINT32 i386_get_stack_segment(i386_state* cpustate, UINT8 privilege)
{
UINT32 ret;
if(privilege >= 3)
}
/* Retrieves the stack pointer located in the current TSS */
-UINT32 i386_get_stack_ptr(i386_state* cpustate, UINT8 privilege)
+static UINT32 i386_get_stack_ptr(i386_state* cpustate, UINT8 privilege)
{
UINT32 ret;
if(privilege >= 3)
if(fault) *fault = false;
}
-extern void i80386_cpu_reset_main(i386_state *cpustate);
-
-static CPU_TRANSLATE( i386 )
-{
- i386_state *cpustate = (i386_state *)cpudevice;
- int ret = TRUE;
- if(space == AS_PROGRAM)
- ret = i386_translate_address(cpustate, intention, address, NULL);
- *address &= cpustate->a20_mask;
- return ret;
-}
-
-void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level)
+static void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level)
{
/* I386 Interrupts/Traps/Faults:
*
if(trap_level >= 3)
{
logerror("IRQ: Triple fault. CPU reset.\n");
- i80386_cpu_reset_main(cpustate);
+ CPU_RESET_CALL(CPU_MODEL);
cpustate->shutdown = 1;
return;
}
}
-void i386_trap_with_error(i386_state *cpustate,int irq, int irq_gate, int trap_level, UINT32 error)
+static void i386_trap_with_error(i386_state *cpustate,int irq, int irq_gate, int trap_level, UINT32 error)
{
i386_trap(cpustate,irq,irq_gate,trap_level);
if(irq == 8 || irq == 10 || irq == 11 || irq == 12 || irq == 13 || irq == 14)
// printf("386 Task Switch from selector %04x to %04x\n",old_task,selector);
}
+static void i386_check_irq_line(i386_state *cpustate)
+{
+ if(!cpustate->smm && cpustate->smi)
+ {
+ pentium_smi(cpustate);
+ return;
+ }
+
+ /* Check if the interrupts are enabled */
+ if ( (cpustate->irq_state) && cpustate->IF )
+ {
+ cpustate->cycles -= 2;
+ i386_trap(cpustate, cpustate->pic->get_intr_ack(), 1, 0);
+ cpustate->irq_state = 0;
+ }
+}
static void i386_protected_mode_jump(i386_state *cpustate, UINT16 seg, UINT32 off, int indirect, int operand32)
{
}
}
-void i386_build_cycle_table()
+static void build_cycle_table()
{
int i, j;
for (j=0; j < X86_NUM_CPUS; j++)
i386_trap(cpustate, 6, 0, 0);
}
+/* Forward declarations */
static void I386OP(decode_opcode)(i386_state *cpustate);
static void I386OP(decode_two_byte)(i386_state *cpustate);
static void I386OP(decode_three_byte38)(i386_state *cpustate);
static void I386OP(decode_four_byte3af2)(i386_state *cpustate);
static void I386OP(decode_four_byte38f3)(i386_state *cpustate);
+
+
#include "i386ops.c"
#include "i386op16.c"
#include "i386op32.c"
#include "pentops.c"
#include "x87ops.c"
#include "i386ops.h"
-#include "i386ops_tbl.h"
-static void i386_set_irq_line(i386_state *cpustate,int irqline, int state)
-{
- if (state != CLEAR_LINE && cpustate->halted)
- {
- cpustate->halted = 0;
- }
-
- if ( irqline == INPUT_LINE_NMI )
- {
- /* NMI (I do not think that this is 100% right) */
- if(cpustate->nmi_masked)
- {
- cpustate->nmi_latched = true;
- return;
- }
- if ( state )
- i386_trap(cpustate,2, 1, 0);
- }
- else
- {
- cpustate->irq_state = state;
- }
-}
-
-static void i386_set_a20_line(i386_state *cpustate,int state)
-{
- if (state)
- {
- cpustate->a20_mask = ~0;
- }
- else
- {
- cpustate->a20_mask = ~(1 << 20);
- }
- // TODO: how does A20M and the tlb interact
- vtlb_flush_dynamic(cpustate->vtlb);
-}
-
-void i386_op_decode_opcode_main(i386_state *cpustate)
+static void I386OP(decode_opcode)(i386_state *cpustate)
{
cpustate->opcode = FETCH(cpustate);
cpustate->opcode_table1_32[cpustate->opcode](cpustate);
else
cpustate->opcode_table1_16[cpustate->opcode](cpustate);
-
}
-void i386_op_decode_two_byte_main(i386_state *cpustate)
+/* Two-byte opcode 0f xx */
+static void I386OP(decode_two_byte)(i386_state *cpustate)
{
cpustate->opcode = FETCH(cpustate);
cpustate->opcode_table2_16[cpustate->opcode](cpustate);
}
-static void I386OP(decode_opcode)(i386_state *cpustate)
-{
- i386_op_decode_opcode_main(cpustate);
-}
-
-/* Two-byte opcode 0f xx */
-static void I386OP(decode_two_byte)(i386_state *cpustate)
-{
- i386_op_decode_two_byte_main(cpustate);
-}
-
-
/* Three-byte opcode 0f 38 xx */
static void I386OP(decode_three_byte38)(i386_state *cpustate)
{
- i386_op_decode_three_byte38_main(cpustate);
-}
-
-void i386_op_decode_three_byte38_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
/* Three-byte opcode 0f 3a xx */
static void I386OP(decode_three_byte3a)(i386_state *cpustate)
{
- i386_op_decode_three_byte3a_main(cpustate);
-}
-
-void i386_op_decode_three_byte3a_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
/* Three-byte opcode prefix 66 0f xx */
static void I386OP(decode_three_byte66)(i386_state *cpustate)
{
- i386_op_decode_three_byte66_main(cpustate);
-}
-
-void i386_op_decode_three_byte66_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if( cpustate->operand_size )
cpustate->opcode_table366_32[cpustate->opcode](cpustate);
/* Three-byte opcode prefix f2 0f xx */
static void I386OP(decode_three_bytef2)(i386_state *cpustate)
{
- i386_op_decode_three_bytef2_main(cpustate);
-}
-
-void i386_op_decode_three_bytef2_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if( cpustate->operand_size )
cpustate->opcode_table3f2_32[cpustate->opcode](cpustate);
/* Three-byte opcode prefix f3 0f */
static void I386OP(decode_three_bytef3)(i386_state *cpustate)
{
- i386_op_decode_three_bytef3_main(cpustate);
-}
-
-void i386_op_decode_three_bytef3_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if( cpustate->operand_size )
cpustate->opcode_table3f3_32[cpustate->opcode](cpustate);
else
cpustate->opcode_table3f3_16[cpustate->opcode](cpustate);
}
+
/* Four-byte opcode prefix 66 0f 38 xx */
static void I386OP(decode_four_byte3866)(i386_state *cpustate)
{
- i386_op_decode_four_byte3866_main(cpustate);
-}
-
-void i386_op_decode_four_byte3866_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
cpustate->opcode_table46638_32[cpustate->opcode](cpustate);
/* Four-byte opcode prefix 66 0f 3a xx */
static void I386OP(decode_four_byte3a66)(i386_state *cpustate)
{
- i386_op_decode_four_byte3a66_main(cpustate);
-}
-
-void i386_op_decode_four_byte3a66_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
cpustate->opcode_table4663a_32[cpustate->opcode](cpustate);
/* Four-byte opcode prefix f2 0f 38 xx */
static void I386OP(decode_four_byte38f2)(i386_state *cpustate)
{
- i386_op_decode_four_byte38f2_main(cpustate);
-}
-
-void i386_op_decode_four_byte38f2_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
cpustate->opcode_table4f238_32[cpustate->opcode](cpustate);
/* Four-byte opcode prefix f2 0f 3a xx */
static void I386OP(decode_four_byte3af2)(i386_state *cpustate)
{
- i386_op_decode_four_byte3af2_main(cpustate);
-}
-void i386_op_decode_four_byte3af2_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
cpustate->opcode_table4f23a_32[cpustate->opcode](cpustate);
/* Four-byte opcode prefix f3 0f 38 xx */
static void I386OP(decode_four_byte38f3)(i386_state *cpustate)
{
- i386_op_decode_four_byte38f3_main(cpustate);
-}
-
-void i386_op_decode_four_byte38f3_main(i386_state *cpustate)
-{
cpustate->opcode = FETCH(cpustate);
if (cpustate->operand_size)
cpustate->opcode_table4f338_32[cpustate->opcode](cpustate);
cpustate->opcode_table4f338_16[cpustate->opcode](cpustate);
}
-void i386_build_opcode_table(i386_state *cpustate, UINT32 features)
+
+/*************************************************************************/
+
+static void i386_postload(i386_state *cpustate)
+{
+ int i;
+ for (i = 0; i < 6; i++)
+ i386_load_segment_descriptor(cpustate,i);
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+static i386_state *i386_common_init(int tlbsize)
+{
+ int i, j;
+ static const int regs8[8] = {AL,CL,DL,BL,AH,CH,DH,BH};
+ static const int regs16[8] = {AX,CX,DX,BX,SP,BP,SI,DI};
+ static const int regs32[8] = {EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI};
+ i386_state *cpustate = (i386_state *)malloc(sizeof(i386_state));
+
+ assert((sizeof(XMM_REG)/sizeof(double)) == 2);
+
+ build_cycle_table();
+
+ for( i=0; i < 256; i++ ) {
+ int c=0;
+ for( j=0; j < 8; j++ ) {
+ if( i & (1 << j) )
+ c++;
+ }
+ i386_parity_table[i] = ~(c & 0x1) & 0x1;
+ }
+
+ for( i=0; i < 256; i++ ) {
+ i386_MODRM_table[i].reg.b = regs8[(i >> 3) & 0x7];
+ i386_MODRM_table[i].reg.w = regs16[(i >> 3) & 0x7];
+ i386_MODRM_table[i].reg.d = regs32[(i >> 3) & 0x7];
+
+ i386_MODRM_table[i].rm.b = regs8[i & 0x7];
+ i386_MODRM_table[i].rm.w = regs16[i & 0x7];
+ i386_MODRM_table[i].rm.d = regs32[i & 0x7];
+ }
+
+ cpustate->vtlb = vtlb_alloc(cpustate, AS_PROGRAM, 0, tlbsize);
+ cpustate->smi = false;
+ cpustate->lock = false;
+
+// i386_interface *intf = (i386_interface *) device->static_config();
+//
+// if (intf != NULL)
+// cpustate->smiact.resolve(intf->smiact, *device);
+// else
+// memset(&cpustate->smiact, 0, sizeof(cpustate->smiact));
+
+ zero_state(cpustate);
+
+ return cpustate;
+}
+
+CPU_INIT( i386 )
+{
+ i386_state *cpustate = i386_common_init(32);
+ build_opcode_table(cpustate, OP_I386);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386];
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386];
+ return cpustate;
+}
+
+static void build_opcode_table(i386_state *cpustate, UINT32 features)
{
int i;
for (i=0; i < 256; i++)
}
}
-void i386_i386_cpu_init_main(i386_state *cpustate)
-{
- i386_build_opcode_table(cpustate, OP_I386);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I386];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I386];
+static void zero_state(i386_state *cpustate)
+{
+ memset( &cpustate->reg, 0, sizeof(cpustate->reg) );
+ memset( cpustate->sreg, 0, sizeof(cpustate->sreg) );
+ cpustate->eip = 0;
+ cpustate->pc = 0;
+ cpustate->prev_eip = 0;
+ cpustate->eflags = 0;
+ cpustate->eflags_mask = 0;
+ cpustate->CF = 0;
+ cpustate->DF = 0;
+ cpustate->SF = 0;
+ cpustate->OF = 0;
+ cpustate->ZF = 0;
+ cpustate->PF = 0;
+ cpustate->AF = 0;
+ cpustate->IF = 0;
+ cpustate->TF = 0;
+ cpustate->IOP1 = 0;
+ cpustate->IOP2 = 0;
+ cpustate->NT = 0;
+ cpustate->RF = 0;
+ cpustate->VM = 0;
+ cpustate->AC = 0;
+ cpustate->VIF = 0;
+ cpustate->VIP = 0;
+ cpustate->ID = 0;
+ cpustate->CPL = 0;
+ cpustate->performed_intersegment_jump = 0;
+ cpustate->delayed_interrupt_enable = 0;
+ memset( cpustate->cr, 0, sizeof(cpustate->cr) );
+ memset( cpustate->dr, 0, sizeof(cpustate->dr) );
+ memset( cpustate->tr, 0, sizeof(cpustate->tr) );
+ memset( &cpustate->gdtr, 0, sizeof(cpustate->gdtr) );
+ memset( &cpustate->idtr, 0, sizeof(cpustate->idtr) );
+ memset( &cpustate->task, 0, sizeof(cpustate->task) );
+ memset( &cpustate->ldtr, 0, sizeof(cpustate->ldtr) );
+ cpustate->ext = 0;
+ cpustate->halted = 0;
+ cpustate->operand_size = 0;
+ cpustate->xmm_operand_size = 0;
+ cpustate->address_size = 0;
+ cpustate->operand_prefix = 0;
+ cpustate->address_prefix = 0;
+ cpustate->segment_prefix = 0;
+ cpustate->segment_override = 0;
+ cpustate->cycles = 0;
+ cpustate->base_cycles = 0;
+ cpustate->opcode = 0;
+ cpustate->irq_state = 0;
+ cpustate->a20_mask = 0;
+ cpustate->cpuid_max_input_value_eax = 0;
+ cpustate->cpuid_id0 = 0;
+ cpustate->cpuid_id1 = 0;
+ cpustate->cpuid_id2 = 0;
+ cpustate->cpu_version = 0;
+ cpustate->feature_flags = 0;
+ cpustate->tsc = 0;
+ cpustate->perfctr[0] = cpustate->perfctr[1] = 0;
+ memset( cpustate->x87_reg, 0, sizeof(cpustate->x87_reg) );
+ cpustate->x87_cw = 0;
+ cpustate->x87_sw = 0;
+ cpustate->x87_tw = 0;
+ cpustate->x87_data_ptr = 0;
+ cpustate->x87_inst_ptr = 0;
+ cpustate->x87_opcode = 0;
+ memset( cpustate->sse_reg, 0, sizeof(cpustate->sse_reg) );
+ cpustate->mxcsr = 0;
+ cpustate->smm = false;
+ cpustate->smi = false;
+ cpustate->smi_latched = false;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+ cpustate->smbase = 0;
+#ifdef DEBUG_MISSING_OPCODE
+ memset( cpustate->opcode_bytes, 0, sizeof(cpustate->opcode_bytes) );
+ cpustate->opcode_pc = 0;
+ cpustate->opcode_bytes_length = 0;
+#endif
}
-void i386_i486_cpu_init_main(i386_state *cpustate)
+static CPU_RESET( i386 )
{
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486);
- build_x87_opcode_table(cpustate);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I486];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I486];
-}
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
-void i386_pentium_cpu_init_main(i386_state *cpustate)
-{
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM);
- build_x87_opcode_table(cpustate);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM];
-}
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x9b;
+ cpustate->sreg[CS].valid = true;
-void i386_mediagx_cpu_init_main(i386_state *cpustate)
-{
- build_x87_opcode_table(cpustate);
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_CYRIX);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_MEDIAGX];
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_MEDIAGX];
-}
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+ cpustate->sreg[DS].valid = cpustate->sreg[ES].valid = cpustate->sreg[FS].valid = cpustate->sreg[GS].valid = cpustate->sreg[SS].valid =true;
-void i386_pentium_pro_cpu_init_main(i386_state *cpustate)
-{
- build_x87_opcode_table(cpustate);
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-}
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
-void i386_pentium_mmx_cpu_init_main(i386_state *cpustate)
-{
- build_x87_opcode_table(cpustate);
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_MMX);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-}
+ cpustate->a20_mask = ~0;
-void i386_pentium2_cpu_init_main(i386_state *cpustate)
-{
- build_x87_opcode_table(cpustate);
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-}
+ cpustate->cr[0] = 0x7fffffe0; // reserved bits set to 1
+ cpustate->eflags = 0;
+ cpustate->eflags_mask = 0x00037fd7;
+ cpustate->eip = 0xfff0;
-void i386_pentium3_cpu_init_main(i386_state *cpustate)
-{
- build_x87_opcode_table(cpustate);
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-}
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 3 (386), Model 0 (DX), Stepping 8 (D1)
+ REG32(EAX) = 0;
+ REG32(EDX) = (3 << 8) | (0 << 4) | (8);
-void i386_pentium4_cpu_init_main(i386_state *cpustate)
-{
- build_x87_opcode_table(cpustate);
- i386_build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE | OP_SSE2);
- cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
- cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
-}
+ cpustate->CPL = 0;
-static void pentium_smi(i386_state *cpustate)
-{
- i386_pentium_smi_main(cpustate);
+ CHANGE_PC(cpustate,cpustate->eip);
}
-void i386_pentium_smi_main(i386_state *cpustate)
+static void pentium_smi(i386_state *cpustate)
{
UINT32 smram_state = cpustate->smbase + 0xfe00;
UINT32 old_cr0 = cpustate->cr[0];
cpustate->nmi_masked = true;
CHANGE_PC(cpustate,cpustate->eip);
}
+
+static void i386_set_irq_line(i386_state *cpustate,int irqline, int state)
+{
+ if (state != CLEAR_LINE && cpustate->halted)
+ {
+ cpustate->halted = 0;
+ }
+
+ if ( irqline == INPUT_LINE_NMI )
+ {
+ /* NMI (I do not think that this is 100% right) */
+ if(cpustate->nmi_masked)
+ {
+ cpustate->nmi_latched = true;
+ return;
+ }
+ if ( state )
+ i386_trap(cpustate,2, 1, 0);
+ }
+ else
+ {
+ cpustate->irq_state = state;
+ }
+}
+
+static void i386_set_a20_line(i386_state *cpustate,int state)
+{
+ if (state)
+ {
+ cpustate->a20_mask = ~0;
+ }
+ else
+ {
+ cpustate->a20_mask = ~(1 << 20);
+ }
+ // TODO: how does A20M and the tlb interact
+ vtlb_flush_dynamic(cpustate->vtlb);
+}
+
+static CPU_EXECUTE( i386 )
+{
+ CHANGE_PC(cpustate,cpustate->eip);
+
+ if (cpustate->halted || cpustate->busreq)
+ {
+#ifdef SINGLE_MODE_DMA
+ if(cpustate->dma != NULL) {
+ cpustate->dma->do_dma();
+ }
+#endif
+ if (cycles == -1) {
+ int passed_cycles = max(1, cpustate->extra_cycles);
+ // this is main cpu, cpustate->cycles is not used
+ /*cpustate->cycles = */cpustate->extra_cycles = 0;
+ cpustate->tsc += passed_cycles;
+ return passed_cycles;
+ } else {
+ cpustate->cycles += cycles;
+ cpustate->base_cycles = cpustate->cycles;
+
+ /* adjust for any interrupts that came in */
+ cpustate->cycles -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
+
+ /* if busreq is raised, spin cpu while remained clock */
+ if (cpustate->cycles > 0) {
+ cpustate->cycles = 0;
+ }
+ int passed_cycles = cpustate->base_cycles - cpustate->cycles;
+ cpustate->tsc += passed_cycles;
+ return passed_cycles;
+ }
+ }
+
+ if (cycles == -1) {
+ cpustate->cycles = 1;
+ } else {
+ cpustate->cycles += cycles;
+ }
+ cpustate->base_cycles = cpustate->cycles;
+
+ /* adjust for any interrupts that came in */
+ cpustate->cycles -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
+
+ while( cpustate->cycles > 0 && !cpustate->busreq )
+ {
+#ifdef USE_DEBUGGER
+ bool now_debugging = cpustate->debugger->now_debugging;
+ if(now_debugging) {
+ cpustate->debugger->check_break_points(cpustate->pc);
+ if(cpustate->debugger->now_suspended) {
+ cpustate->emu->mute_sound();
+ while(cpustate->debugger->now_debugging && cpustate->debugger->now_suspended) {
+ cpustate->emu->sleep(10);
+ }
+ }
+ if(cpustate->debugger->now_debugging) {
+ cpustate->program = cpustate->io = cpustate->debugger;
+ } else {
+ now_debugging = false;
+ }
+ i386_check_irq_line(cpustate);
+ cpustate->operand_size = cpustate->sreg[CS].d;
+ cpustate->xmm_operand_size = 0;
+ cpustate->address_size = cpustate->sreg[CS].d;
+ cpustate->operand_prefix = 0;
+ cpustate->address_prefix = 0;
+
+ cpustate->ext = 1;
+ int old_tf = cpustate->TF;
+
+ cpustate->segment_prefix = 0;
+ cpustate->prev_eip = cpustate->eip;
+ cpustate->prev_pc = cpustate->pc;
+
+ if(cpustate->delayed_interrupt_enable != 0)
+ {
+ cpustate->IF = 1;
+ cpustate->delayed_interrupt_enable = 0;
+ }
+#ifdef DEBUG_MISSING_OPCODE
+ cpustate->opcode_bytes_length = 0;
+ cpustate->opcode_pc = cpustate->pc;
+#endif
+ try
+ {
+ I386OP(decode_opcode)(cpustate);
+ if(cpustate->TF && old_tf)
+ {
+ cpustate->prev_eip = cpustate->eip;
+ cpustate->ext = 1;
+ i386_trap(cpustate,1,0,0);
+ }
+ if(cpustate->lock && (cpustate->opcode != 0xf0))
+ cpustate->lock = false;
+ }
+ catch(UINT64 e)
+ {
+ cpustate->ext = 1;
+ i386_trap_with_error(cpustate,e&0xffffffff,0,0,e>>32);
+ }
+#ifdef SINGLE_MODE_DMA
+ if(cpustate->dma != NULL) {
+ cpustate->dma->do_dma();
+ }
+#endif
+ /* adjust for any interrupts that came in */
+ cpustate->cycles -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
+
+ if(now_debugging) {
+ if(!cpustate->debugger->now_going) {
+ cpustate->debugger->now_suspended = true;
+ }
+ cpustate->program = cpustate->program_stored;
+ cpustate->io = cpustate->io_stored;
+ }
+ } else {
+#endif
+ i386_check_irq_line(cpustate);
+ cpustate->operand_size = cpustate->sreg[CS].d;
+ cpustate->xmm_operand_size = 0;
+ cpustate->address_size = cpustate->sreg[CS].d;
+ cpustate->operand_prefix = 0;
+ cpustate->address_prefix = 0;
+
+ cpustate->ext = 1;
+ int old_tf = cpustate->TF;
+
+ cpustate->segment_prefix = 0;
+ cpustate->prev_eip = cpustate->eip;
+ cpustate->prev_pc = cpustate->pc;
+
+ if(cpustate->delayed_interrupt_enable != 0)
+ {
+ cpustate->IF = 1;
+ cpustate->delayed_interrupt_enable = 0;
+ }
+#ifdef DEBUG_MISSING_OPCODE
+ cpustate->opcode_bytes_length = 0;
+ cpustate->opcode_pc = cpustate->pc;
+#endif
+ try
+ {
+ I386OP(decode_opcode)(cpustate);
+ if(cpustate->TF && old_tf)
+ {
+ cpustate->prev_eip = cpustate->eip;
+ cpustate->ext = 1;
+ i386_trap(cpustate,1,0,0);
+ }
+ if(cpustate->lock && (cpustate->opcode != 0xf0))
+ cpustate->lock = false;
+ }
+ catch(UINT64 e)
+ {
+ cpustate->ext = 1;
+ i386_trap_with_error(cpustate,e&0xffffffff,0,0,e>>32);
+ }
+#ifdef SINGLE_MODE_DMA
+ if(cpustate->dma != NULL) {
+ cpustate->dma->do_dma();
+ }
+#endif
+ /* adjust for any interrupts that came in */
+ cpustate->cycles -= cpustate->extra_cycles;
+ cpustate->extra_cycles = 0;
+#ifdef USE_DEBUGGER
+ }
+#endif
+ }
+
+ /* if busreq is raised, spin cpu while remained clock */
+ if (cpustate->cycles > 0 && cpustate->busreq) {
+ cpustate->cycles = 0;
+ }
+ int passed_cycles = cpustate->base_cycles - cpustate->cycles;
+ cpustate->tsc += passed_cycles;
+ return passed_cycles;
+}
+
+/*************************************************************************/
+
+static CPU_TRANSLATE( i386 )
+{
+ i386_state *cpustate = (i386_state *)cpudevice;
+ int ret = TRUE;
+ if(space == AS_PROGRAM)
+ ret = i386_translate_address(cpustate, intention, address, NULL);
+ *address &= cpustate->a20_mask;
+ return ret;
+}
+
+/*****************************************************************************/
+/* Intel 486 */
+
+
+static CPU_INIT( i486 )
+{
+ i386_state *cpustate = i386_common_init(32);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486);
+ build_x87_opcode_table(cpustate);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_I486];
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_I486];
+ return cpustate;
+}
+
+static CPU_RESET( i486 )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x00000010;
+ cpustate->eflags = 0;
+ cpustate->eflags_mask = 0x00077fd7;
+ cpustate->eip = 0xfff0;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 4 (486), Model 0/1 (DX), Stepping 3
+ REG32(EAX) = 0;
+ REG32(EDX) = (4 << 8) | (0 << 4) | (3);
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Pentium */
+
+
+static CPU_INIT( pentium )
+{
+ // 64 dtlb small, 8 dtlb large, 32 itlb
+ i386_state *cpustate = i386_common_init(96);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM);
+ build_x87_opcode_table(cpustate);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM];
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM];
+ return cpustate;
+}
+
+static CPU_RESET( pentium )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x00000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x003f7fd7;
+ cpustate->eip = 0xfff0;
+ cpustate->mxcsr = 0x1f80;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->smbase = 0x30000;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 5 (Pentium), Model 2 (75 - 200MHz), Stepping 5
+ REG32(EAX) = 0;
+ REG32(EDX) = (5 << 8) | (2 << 4) | (5);
+
+ cpustate->cpuid_id0 = 0x756e6547; // Genu
+ cpustate->cpuid_id1 = 0x49656e69; // ineI
+ cpustate->cpuid_id2 = 0x6c65746e; // ntel
+
+ cpustate->cpuid_max_input_value_eax = 0x01;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ // [ 2:2] I/O breakpoints
+ // [ 4:4] Time Stamp Counter
+ // [ 5:5] Pentium CPU style model specific registers
+ // [ 7:7] Machine Check Exception
+ // [ 8:8] CMPXCHG8B instruction
+ cpustate->feature_flags = 0x000001bf;
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Cyrix MediaGX */
+
+
+static CPU_INIT( mediagx )
+{
+ // probably 32 unified
+ i386_state *cpustate = i386_common_init(32);
+ build_x87_opcode_table(cpustate);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_CYRIX);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_MEDIAGX];
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_MEDIAGX];
+ return cpustate;
+}
+
+static CPU_RESET( mediagx )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x00000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ cpustate->eip = 0xfff0;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 4, Model 4 (MediaGX)
+ REG32(EAX) = 0;
+ REG32(EDX) = (4 << 8) | (4 << 4) | (1); /* TODO: is this correct? */
+
+ cpustate->cpuid_id0 = 0x69727943; // Cyri
+ cpustate->cpuid_id1 = 0x736e4978; // xIns
+ cpustate->cpuid_id2 = 0x6d616574; // tead
+
+ cpustate->cpuid_max_input_value_eax = 0x01;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ cpustate->feature_flags = 0x00000001;
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Intel Pentium Pro */
+
+static CPU_INIT( pentium_pro )
+{
+ // 64 dtlb small, 32 itlb
+ i386_state *cpustate = i386_common_init(96);
+ build_x87_opcode_table(cpustate);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ return cpustate;
+}
+
+static CPU_RESET( pentium_pro )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x60000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ cpustate->eip = 0xfff0;
+ cpustate->mxcsr = 0x1f80;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->smbase = 0x30000;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 6, Model 1 (Pentium Pro)
+ REG32(EAX) = 0;
+ REG32(EDX) = (6 << 8) | (1 << 4) | (1); /* TODO: is this correct? */
+
+ cpustate->cpuid_id0 = 0x756e6547; // Genu
+ cpustate->cpuid_id1 = 0x49656e69; // ineI
+ cpustate->cpuid_id2 = 0x6c65746e; // ntel
+
+ cpustate->cpuid_max_input_value_eax = 0x02;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ // [ 2:2] I/O breakpoints
+ // [ 4:4] Time Stamp Counter
+ // [ 5:5] Pentium CPU style model specific registers
+ // [ 7:7] Machine Check Exception
+ // [ 8:8] CMPXCHG8B instruction
+ // [15:15] CMOV and FCMOV
+ // No MMX
+ cpustate->feature_flags = 0x000081bf;
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Intel Pentium MMX */
+
+static CPU_INIT( pentium_mmx )
+{
+ // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
+ i386_state *cpustate = i386_common_init(96);
+ build_x87_opcode_table(cpustate);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_MMX);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ return cpustate;
+}
+
+static CPU_RESET( pentium_mmx )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x60000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ cpustate->eip = 0xfff0;
+ cpustate->mxcsr = 0x1f80;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->smbase = 0x30000;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 5, Model 4 (P55C)
+ REG32(EAX) = 0;
+ REG32(EDX) = (5 << 8) | (4 << 4) | (1);
+
+ cpustate->cpuid_id0 = 0x756e6547; // Genu
+ cpustate->cpuid_id1 = 0x49656e69; // ineI
+ cpustate->cpuid_id2 = 0x6c65746e; // ntel
+
+ cpustate->cpuid_max_input_value_eax = 0x01;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ // [ 2:2] I/O breakpoints
+ // [ 4:4] Time Stamp Counter
+ // [ 5:5] Pentium CPU style model specific registers
+ // [ 7:7] Machine Check Exception
+ // [ 8:8] CMPXCHG8B instruction
+ // [23:23] MMX instructions
+ cpustate->feature_flags = 0x008001bf;
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Intel Pentium II */
+
+static CPU_INIT( pentium2 )
+{
+ // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
+ i386_state *cpustate = i386_common_init(96);
+ build_x87_opcode_table(cpustate);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ return cpustate;
+}
+
+static CPU_RESET( pentium2 )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x60000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ cpustate->eip = 0xfff0;
+ cpustate->mxcsr = 0x1f80;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->smbase = 0x30000;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 6, Model 3 (Pentium II / Klamath)
+ REG32(EAX) = 0;
+ REG32(EDX) = (6 << 8) | (3 << 4) | (1); /* TODO: is this correct? */
+
+ cpustate->cpuid_id0 = 0x756e6547; // Genu
+ cpustate->cpuid_id1 = 0x49656e69; // ineI
+ cpustate->cpuid_id2 = 0x6c65746e; // ntel
+
+ cpustate->cpuid_max_input_value_eax = 0x02;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ cpustate->feature_flags = 0x008081bf; // TODO: enable relevant flags here
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Intel Pentium III */
+
+static CPU_INIT( pentium3 )
+{
+ // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
+ i386_state *cpustate = i386_common_init(96);
+ build_x87_opcode_table(cpustate);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ return cpustate;
+}
+
+static CPU_RESET( pentium3 )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x60000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ cpustate->eip = 0xfff0;
+ cpustate->mxcsr = 0x1f80;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->smbase = 0x30000;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [11:8] Family
+ // [ 7:4] Model
+ // [ 3:0] Stepping ID
+ // Family 6, Model 8 (Pentium III / Coppermine)
+ REG32(EAX) = 0;
+ REG32(EDX) = (6 << 8) | (8 << 4) | (10);
+
+ cpustate->cpuid_id0 = 0x756e6547; // Genu
+ cpustate->cpuid_id1 = 0x49656e69; // ineI
+ cpustate->cpuid_id2 = 0x6c65746e; // ntel
+
+ cpustate->cpuid_max_input_value_eax = 0x03;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ // [ 4:4] Time Stamp Counter
+ // [ D:D] PTE Global Bit
+ cpustate->feature_flags = 0x00002011; // TODO: enable relevant flags here
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+/*****************************************************************************/
+/* Intel Pentium 4 */
+
+static CPU_INIT( pentium4 )
+{
+ // 128 dtlb, 64 itlb
+ i386_state *cpustate = i386_common_init(196);
+ build_x87_opcode_table(cpustate);
+ build_opcode_table(cpustate, OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE | OP_SSE2);
+ cpustate->cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ cpustate->cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM]; // TODO: generate own cycle tables
+ return cpustate;
+}
+
+static CPU_RESET( pentium4 )
+{
+ zero_state(cpustate);
+ vtlb_flush_dynamic(cpustate->vtlb);
+
+ cpustate->sreg[CS].selector = 0xf000;
+ cpustate->sreg[CS].base = 0xffff0000;
+ cpustate->sreg[CS].limit = 0xffff;
+ cpustate->sreg[CS].flags = 0x009b;
+
+ cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
+ cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
+ cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
+
+ cpustate->idtr.base = 0;
+ cpustate->idtr.limit = 0x3ff;
+
+ cpustate->a20_mask = ~0;
+
+ cpustate->cr[0] = 0x60000010;
+ cpustate->eflags = 0x00200000;
+ cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
+ cpustate->eip = 0xfff0;
+ cpustate->mxcsr = 0x1f80;
+ cpustate->smm = false;
+ cpustate->smi_latched = false;
+ cpustate->smbase = 0x30000;
+ cpustate->nmi_masked = false;
+ cpustate->nmi_latched = false;
+
+ x87_reset(cpustate);
+
+ // [27:20] Extended family
+ // [19:16] Extended model
+ // [13:12] Type
+ // [11: 8] Family
+ // [ 7: 4] Model
+ // [ 3: 0] Stepping ID
+ // Family 15, Model 0 (Pentium 4 / Willamette)
+ REG32(EAX) = 0;
+ REG32(EDX) = (0 << 20) | (0xf << 8) | (0 << 4) | (1);
+
+ cpustate->cpuid_id0 = 0x756e6547; // Genu
+ cpustate->cpuid_id1 = 0x49656e69; // ineI
+ cpustate->cpuid_id2 = 0x6c65746e; // ntel
+
+ cpustate->cpuid_max_input_value_eax = 0x02;
+ cpustate->cpu_version = REG32(EDX);
+
+ // [ 0:0] FPU on chip
+ cpustate->feature_flags = 0x00000001; // TODO: enable relevant flags here
+
+ CHANGE_PC(cpustate,cpustate->eip);
+}
+
+++ /dev/null
-#include "i386priv.h"
-
-extern UINT32 i386_load_protected_mode_segment(i386_state *cpustate, I386_SREG *seg, UINT64 *desc );
-extern void i386_load_call_gate(i386_state* cpustate, I386_CALL_GATE *gate);
-extern void i386_set_descriptor_accessed(i386_state *cpustate, UINT16 selector);
-extern void i386_load_segment_descriptor(i386_state *cpustate, int segment );
-extern UINT32 i386_get_stack_segment(i386_state* cpustate, UINT8 privilege);
-extern UINT32 i386_get_stack_ptr(i386_state* cpustate, UINT8 privilege);
-extern void i386_build_cycle_table();
-
-extern void i386_build_opcode_table(i386_state *cpustate, UINT32 features);
-static void zero_state(i386_state *cpustate);
-
-extern int x87_inc_stack(i386_state *cpustate);
-extern int x87_dec_stack(i386_state *cpustate);
-extern int x87_check_exceptions(i386_state *cpustate);
-extern void x87_reset(i386_state *cpustate);
-extern void build_x87_opcode_table(i386_state *cpustate);
-
-extern void i386_op_decode_opcode_main(i386_state *cpustate);
-extern void i386_op_decode_two_byte_main(i386_state *cpustate);
-extern void i386_op_decode_three_byte38_main(i386_state *cpustate);
-extern void i386_op_decode_three_byte3a_main(i386_state *cpustate);
-extern void i386_op_decode_three_byte66_main(i386_state *cpustate);
-extern void i386_op_decode_three_bytef2_main(i386_state *cpustate);
-extern void i386_op_decode_three_bytef3_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte3866_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte38f2_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte38f3_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte3a66_main(i386_state *cpustate);
-extern void i386_op_decode_four_byte3af2_main(i386_state *cpustate);
-
-static void I386OP(decode_opcode)(i386_state *cpustate);
-static void I386OP(decode_two_byte)(i386_state *cpustate);
-static void I386OP(decode_three_byte38)(i386_state *cpustate);
-static void I386OP(decode_three_byte3a)(i386_state *cpustate);
-static void I386OP(decode_three_byte66)(i386_state *cpustate);
-static void I386OP(decode_three_bytef2)(i386_state *cpustate);
-static void I386OP(decode_three_bytef3)(i386_state *cpustate);
-static void I386OP(decode_four_byte3866)(i386_state *cpustate);
-static void I386OP(decode_four_byte3a66)(i386_state *cpustate);
-static void I386OP(decode_four_byte38f2)(i386_state *cpustate);
-static void I386OP(decode_four_byte3af2)(i386_state *cpustate);
-static void I386OP(decode_four_byte38f3)(i386_state *cpustate);
-
-extern void i386_i386_cpu_init_main(i386_state *cpustate);
-extern void i386_i486_cpu_init_main(i386_state *cpustate);
-extern void i386_pentium_cpu_init_main(i386_state *cpustate);
-extern void i386_pentium_pro_cpu_init_main(i386_state *cpustate);
-extern void i386_mediagx_cpu_init_main(i386_state *cpustate);
-extern void i386_pentium_mmx_cpu_init_main(i386_state *cpustate);
-extern void i386_pentium2_cpu_init_main(i386_state *cpustate);
-extern void i386_pentium3_cpu_init_main(i386_state *cpustate);
-extern void i386_pentium4_cpu_init_main(i386_state *cpustate);
-
-
-static CPU_RESET( i386 );
-static CPU_RESET( i486 );
-static CPU_RESET( pentium );
-static CPU_RESET( mediagx );
-static CPU_RESET( pentium_pro );
-static CPU_RESET( pentium_mmx );
-static CPU_RESET( pentium2 );
-static CPU_RESET( pentium3 );
-static CPU_RESET( pentium4 );
-
-extern void i386_pentium_smi_main(i386_state *cpustate);
-static void pentium_smi(i386_state *state);
-/*************************************************************************/
-
-#include "i386ops.h"
-
-extern void i386_trap(i386_state *cpustate,int irq, int irq_gate, int trap_level);
-extern void i386_trap_with_error(i386_state *cpustate,int irq, int irq_gate, int trap_level, UINT32 error);
-
-static UINT32 get_flags(i386_state *cpustate)
-{
- UINT32 f = 0x2;
- f |= cpustate->CF;
- f |= cpustate->PF << 2;
- f |= cpustate->AF << 4;
- f |= cpustate->ZF << 6;
- f |= cpustate->SF << 7;
- f |= cpustate->TF << 8;
- f |= cpustate->IF << 9;
- f |= cpustate->DF << 10;
- f |= cpustate->OF << 11;
- f |= cpustate->IOP1 << 12;
- f |= cpustate->IOP2 << 13;
- f |= cpustate->NT << 14;
- f |= cpustate->RF << 16;
- f |= cpustate->VM << 17;
- f |= cpustate->AC << 18;
- f |= cpustate->VIF << 19;
- f |= cpustate->VIP << 20;
- f |= cpustate->ID << 21;
- return (cpustate->eflags & ~cpustate->eflags_mask) | (f & cpustate->eflags_mask);
-}
-
-static void set_flags(i386_state *cpustate, UINT32 f )
-{
- cpustate->CF = (f & 0x1) ? 1 : 0;
- cpustate->PF = (f & 0x4) ? 1 : 0;
- cpustate->AF = (f & 0x10) ? 1 : 0;
- cpustate->ZF = (f & 0x40) ? 1 : 0;
- cpustate->SF = (f & 0x80) ? 1 : 0;
- cpustate->TF = (f & 0x100) ? 1 : 0;
- cpustate->IF = (f & 0x200) ? 1 : 0;
- cpustate->DF = (f & 0x400) ? 1 : 0;
- cpustate->OF = (f & 0x800) ? 1 : 0;
- cpustate->IOP1 = (f & 0x1000) ? 1 : 0;
- cpustate->IOP2 = (f & 0x2000) ? 1 : 0;
- cpustate->NT = (f & 0x4000) ? 1 : 0;
- cpustate->RF = (f & 0x10000) ? 1 : 0;
- cpustate->VM = (f & 0x20000) ? 1 : 0;
- cpustate->AC = (f & 0x40000) ? 1 : 0;
- cpustate->VIF = (f & 0x80000) ? 1 : 0;
- cpustate->VIP = (f & 0x100000) ? 1 : 0;
- cpustate->ID = (f & 0x200000) ? 1 : 0;
- cpustate->eflags = f & cpustate->eflags_mask;
-}
-
-static void i386_postload(i386_state *cpustate)
-{
- int i;
- for (i = 0; i < 6; i++)
- i386_load_segment_descriptor(cpustate,i);
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-
-extern void i386_op_decode_opcode_main(i386_state *cpustate);
-extern void i386_op_decode_two_byte_main(i386_state *cpustate);
-
-static void I386OP(decode_opcode)(i386_state *cpustate)
-{
- i386_op_decode_opcode_main(cpustate);
-}
-
-/* Two-byte opcode 0f xx */
-static void I386OP(decode_two_byte)(i386_state *cpustate)
-{
- i386_op_decode_two_byte_main(cpustate);
-}
-
-static void I386OP(decode_three_byte38)(i386_state *cpustate)
-{
- i386_op_decode_three_byte38_main(cpustate);
-}
-
-static void I386OP(decode_three_byte3a)(i386_state *cpustate)
-{
- i386_op_decode_three_byte3a_main(cpustate);
-}
-
-static void I386OP(decode_three_byte66)(i386_state *cpustate)
-{
- i386_op_decode_three_byte66_main(cpustate);
-}
-
-static void I386OP(decode_three_bytef2)(i386_state *cpustate)
-{
- i386_op_decode_three_bytef2_main(cpustate);
-}
-
-static void I386OP(decode_three_bytef3)(i386_state *cpustate)
-{
- i386_op_decode_three_bytef3_main(cpustate);
-}
-
-static void I386OP(decode_four_byte3866)(i386_state *cpustate)
-{
- i386_op_decode_four_byte3866_main(cpustate);
-}
-
-static void I386OP(decode_four_byte3a66)(i386_state *cpustate)
-{
- i386_op_decode_four_byte3a66_main(cpustate);
-}
-static void I386OP(decode_four_byte38f2)(i386_state *cpustate)
-{
- i386_op_decode_four_byte38f2_main(cpustate);
-}
-static void I386OP(decode_four_byte3af2)(i386_state *cpustate)
-{
- i386_op_decode_four_byte3af2_main(cpustate);
-}
-static void I386OP(decode_four_byte38f3)(i386_state *cpustate)
-{
- i386_op_decode_four_byte38f3_main(cpustate);
-}
-
-
-static i386_state *i386_common_init(int tlbsize)
-{
- int i, j;
- static const int regs8[8] = {AL,CL,DL,BL,AH,CH,DH,BH};
- static const int regs16[8] = {AX,CX,DX,BX,SP,BP,SI,DI};
- static const int regs32[8] = {EAX,ECX,EDX,EBX,ESP,EBP,ESI,EDI};
- i386_state *cpustate = (i386_state *)malloc(sizeof(i386_state));
-
- assert((sizeof(XMM_REG)/sizeof(double)) == 2);
-
- i386_build_cycle_table();
-
- for( i=0; i < 256; i++ ) {
- int c=0;
- for( j=0; j < 8; j++ ) {
- if( i & (1 << j) )
- c++;
- }
- i386_parity_table[i] = ~(c & 0x1) & 0x1;
- }
-
- for( i=0; i < 256; i++ ) {
- i386_MODRM_table[i].reg.b = regs8[(i >> 3) & 0x7];
- i386_MODRM_table[i].reg.w = regs16[(i >> 3) & 0x7];
- i386_MODRM_table[i].reg.d = regs32[(i >> 3) & 0x7];
-
- i386_MODRM_table[i].rm.b = regs8[i & 0x7];
- i386_MODRM_table[i].rm.w = regs16[i & 0x7];
- i386_MODRM_table[i].rm.d = regs32[i & 0x7];
- }
-
- cpustate->vtlb = vtlb_alloc(cpustate, AS_PROGRAM, 0, tlbsize);
- cpustate->smi = false;
- cpustate->lock = false;
-
-// i386_interface *intf = (i386_interface *) device->static_config();
-//
-// if (intf != NULL)
-// cpustate->smiact.resolve(intf->smiact, *device);
-// else
-// memset(&cpustate->smiact, 0, sizeof(cpustate->smiact));
-
- zero_state(cpustate);
-
- return cpustate;
-}
-static void i386_check_irq_line(i386_state *cpustate)
-{
- if(!cpustate->smm && cpustate->smi)
- {
- pentium_smi(cpustate);
- return;
- }
-
- /* Check if the interrupts are enabled */
- if ( (cpustate->irq_state) && cpustate->IF )
- {
- cpustate->cycles -= 2;
- i386_trap(cpustate, cpustate->pic->get_intr_ack(), 1, 0);
- cpustate->irq_state = 0;
- }
-}
-
-static void zero_state(i386_state *cpustate)
-{
- memset( &cpustate->reg, 0, sizeof(cpustate->reg) );
- memset( cpustate->sreg, 0, sizeof(cpustate->sreg) );
- cpustate->eip = 0;
- cpustate->pc = 0;
- cpustate->prev_eip = 0;
- cpustate->eflags = 0;
- cpustate->eflags_mask = 0;
- cpustate->CF = 0;
- cpustate->DF = 0;
- cpustate->SF = 0;
- cpustate->OF = 0;
- cpustate->ZF = 0;
- cpustate->PF = 0;
- cpustate->AF = 0;
- cpustate->IF = 0;
- cpustate->TF = 0;
- cpustate->IOP1 = 0;
- cpustate->IOP2 = 0;
- cpustate->NT = 0;
- cpustate->RF = 0;
- cpustate->VM = 0;
- cpustate->AC = 0;
- cpustate->VIF = 0;
- cpustate->VIP = 0;
- cpustate->ID = 0;
- cpustate->CPL = 0;
- cpustate->performed_intersegment_jump = 0;
- cpustate->delayed_interrupt_enable = 0;
- memset( cpustate->cr, 0, sizeof(cpustate->cr) );
- memset( cpustate->dr, 0, sizeof(cpustate->dr) );
- memset( cpustate->tr, 0, sizeof(cpustate->tr) );
- memset( &cpustate->gdtr, 0, sizeof(cpustate->gdtr) );
- memset( &cpustate->idtr, 0, sizeof(cpustate->idtr) );
- memset( &cpustate->task, 0, sizeof(cpustate->task) );
- memset( &cpustate->ldtr, 0, sizeof(cpustate->ldtr) );
- cpustate->ext = 0;
- cpustate->halted = 0;
- cpustate->operand_size = 0;
- cpustate->xmm_operand_size = 0;
- cpustate->address_size = 0;
- cpustate->operand_prefix = 0;
- cpustate->address_prefix = 0;
- cpustate->segment_prefix = 0;
- cpustate->segment_override = 0;
- cpustate->cycles = 0;
- cpustate->base_cycles = 0;
- cpustate->opcode = 0;
- cpustate->irq_state = 0;
- cpustate->a20_mask = 0;
- cpustate->cpuid_max_input_value_eax = 0;
- cpustate->cpuid_id0 = 0;
- cpustate->cpuid_id1 = 0;
- cpustate->cpuid_id2 = 0;
- cpustate->cpu_version = 0;
- cpustate->feature_flags = 0;
- cpustate->tsc = 0;
- cpustate->perfctr[0] = cpustate->perfctr[1] = 0;
- memset( cpustate->x87_reg, 0, sizeof(cpustate->x87_reg) );
- cpustate->x87_cw = 0;
- cpustate->x87_sw = 0;
- cpustate->x87_tw = 0;
- cpustate->x87_data_ptr = 0;
- cpustate->x87_inst_ptr = 0;
- cpustate->x87_opcode = 0;
- memset( cpustate->sse_reg, 0, sizeof(cpustate->sse_reg) );
- cpustate->mxcsr = 0;
- cpustate->smm = false;
- cpustate->smi = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
- cpustate->smbase = 0;
-#ifdef DEBUG_MISSING_OPCODE
- memset( cpustate->opcode_bytes, 0, sizeof(cpustate->opcode_bytes) );
- cpustate->opcode_pc = 0;
- cpustate->opcode_bytes_length = 0;
-#endif
-}
-
-
-void i80386_cpu_reset_main(i386_state *cpustate)
-{
- CPU_RESET_CALL(CPU_MODEL);
-}
-
-static CPU_EXECUTE( i386 )
-{
- CHANGE_PC(cpustate,cpustate->eip);
-
- if (cpustate->halted || cpustate->busreq)
- {
-#ifdef SINGLE_MODE_DMA
- if(cpustate->dma != NULL) {
- cpustate->dma->do_dma();
- }
-#endif
- if (cycles == -1) {
- int passed_cycles = max(1, cpustate->extra_cycles);
- // this is main cpu, cpustate->cycles is not used
- /*cpustate->cycles = */cpustate->extra_cycles = 0;
- cpustate->tsc += passed_cycles;
- return passed_cycles;
- } else {
- cpustate->cycles += cycles;
- cpustate->base_cycles = cpustate->cycles;
-
- /* adjust for any interrupts that came in */
- cpustate->cycles -= cpustate->extra_cycles;
- cpustate->extra_cycles = 0;
-
- /* if busreq is raised, spin cpu while remained clock */
- if (cpustate->cycles > 0) {
- cpustate->cycles = 0;
- }
- int passed_cycles = cpustate->base_cycles - cpustate->cycles;
- cpustate->tsc += passed_cycles;
- return passed_cycles;
- }
- }
-
- if (cycles == -1) {
- cpustate->cycles = 1;
- } else {
- cpustate->cycles += cycles;
- }
- cpustate->base_cycles = cpustate->cycles;
-
- /* adjust for any interrupts that came in */
- cpustate->cycles -= cpustate->extra_cycles;
- cpustate->extra_cycles = 0;
-
- while( cpustate->cycles > 0 && !cpustate->busreq )
- {
-#ifdef USE_DEBUGGER
- bool now_debugging = cpustate->debugger->now_debugging;
- if(now_debugging) {
- cpustate->debugger->check_break_points(cpustate->pc);
- if(cpustate->debugger->now_suspended) {
- cpustate->emu->mute_sound();
- while(cpustate->debugger->now_debugging && cpustate->debugger->now_suspended) {
- cpustate->emu->sleep(10);
- }
- }
- if(cpustate->debugger->now_debugging) {
- cpustate->program = cpustate->io = cpustate->debugger;
- } else {
- now_debugging = false;
- }
- i386_check_irq_line(cpustate);
- cpustate->operand_size = cpustate->sreg[CS].d;
- cpustate->xmm_operand_size = 0;
- cpustate->address_size = cpustate->sreg[CS].d;
- cpustate->operand_prefix = 0;
- cpustate->address_prefix = 0;
-
- cpustate->ext = 1;
- int old_tf = cpustate->TF;
-
- cpustate->segment_prefix = 0;
- cpustate->prev_eip = cpustate->eip;
- cpustate->prev_pc = cpustate->pc;
-
- if(cpustate->delayed_interrupt_enable != 0)
- {
- cpustate->IF = 1;
- cpustate->delayed_interrupt_enable = 0;
- }
-#ifdef DEBUG_MISSING_OPCODE
- cpustate->opcode_bytes_length = 0;
- cpustate->opcode_pc = cpustate->pc;
-#endif
- try
- {
- I386OP(decode_opcode)(cpustate);
- if(cpustate->TF && old_tf)
- {
- cpustate->prev_eip = cpustate->eip;
- cpustate->ext = 1;
- i386_trap(cpustate,1,0,0);
- }
- if(cpustate->lock && (cpustate->opcode != 0xf0))
- cpustate->lock = false;
- }
- catch(UINT64 e)
- {
- cpustate->ext = 1;
- i386_trap_with_error(cpustate,e&0xffffffff,0,0,e>>32);
- }
-#ifdef SINGLE_MODE_DMA
- if(cpustate->dma != NULL) {
- cpustate->dma->do_dma();
- }
-#endif
- /* adjust for any interrupts that came in */
- cpustate->cycles -= cpustate->extra_cycles;
- cpustate->extra_cycles = 0;
-
- if(now_debugging) {
- if(!cpustate->debugger->now_going) {
- cpustate->debugger->now_suspended = true;
- }
- cpustate->program = cpustate->program_stored;
- cpustate->io = cpustate->io_stored;
- }
- } else {
-#endif
- i386_check_irq_line(cpustate);
- cpustate->operand_size = cpustate->sreg[CS].d;
- cpustate->xmm_operand_size = 0;
- cpustate->address_size = cpustate->sreg[CS].d;
- cpustate->operand_prefix = 0;
- cpustate->address_prefix = 0;
-
- cpustate->ext = 1;
- int old_tf = cpustate->TF;
-
- cpustate->segment_prefix = 0;
- cpustate->prev_eip = cpustate->eip;
- cpustate->prev_pc = cpustate->pc;
-
- if(cpustate->delayed_interrupt_enable != 0)
- {
- cpustate->IF = 1;
- cpustate->delayed_interrupt_enable = 0;
- }
-#ifdef DEBUG_MISSING_OPCODE
- cpustate->opcode_bytes_length = 0;
- cpustate->opcode_pc = cpustate->pc;
-#endif
- try
- {
- I386OP(decode_opcode)(cpustate);
- if(cpustate->TF && old_tf)
- {
- cpustate->prev_eip = cpustate->eip;
- cpustate->ext = 1;
- i386_trap(cpustate,1,0,0);
- }
- if(cpustate->lock && (cpustate->opcode != 0xf0))
- cpustate->lock = false;
- }
- catch(UINT64 e)
- {
- cpustate->ext = 1;
- i386_trap_with_error(cpustate,e&0xffffffff,0,0,e>>32);
- }
-#ifdef SINGLE_MODE_DMA
- if(cpustate->dma != NULL) {
- cpustate->dma->do_dma();
- }
-#endif
- /* adjust for any interrupts that came in */
- cpustate->cycles -= cpustate->extra_cycles;
- cpustate->extra_cycles = 0;
-#ifdef USE_DEBUGGER
- }
-#endif
- }
-
- /* if busreq is raised, spin cpu while remained clock */
- if (cpustate->cycles > 0 && cpustate->busreq) {
- cpustate->cycles = 0;
- }
- int passed_cycles = cpustate->base_cycles - cpustate->cycles;
- cpustate->tsc += passed_cycles;
- return passed_cycles;
-}
-
-static CPU_INIT( i386 )
-{
- i386_state *cpustate = i386_common_init(32);
- i386_i386_cpu_init_main(cpustate);
- return cpustate;
-}
-/*************************************************************************/
-
-static CPU_RESET( i386 )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x9b;
- cpustate->sreg[CS].valid = true;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
- cpustate->sreg[DS].valid = cpustate->sreg[ES].valid = cpustate->sreg[FS].valid = cpustate->sreg[GS].valid = cpustate->sreg[SS].valid =true;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x7fffffe0; // reserved bits set to 1
- cpustate->eflags = 0;
- cpustate->eflags_mask = 0x00037fd7;
- cpustate->eip = 0xfff0;
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 3 (386), Model 0 (DX), Stepping 8 (D1)
- REG32(EAX) = 0;
- REG32(EDX) = (3 << 8) | (0 << 4) | (8);
-
- cpustate->CPL = 0;
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-/*****************************************************************************/
-/* Intel 486 */
-
-static CPU_RESET( i486 )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x00000010;
- cpustate->eflags = 0;
- cpustate->eflags_mask = 0x00077fd7;
- cpustate->eip = 0xfff0;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 4 (486), Model 0/1 (DX), Stepping 3
- REG32(EAX) = 0;
- REG32(EDX) = (4 << 8) | (0 << 4) | (3);
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-
-static CPU_INIT( i486 )
-{
- i386_state *cpustate = i386_common_init(32);
- i386_i486_cpu_init_main(cpustate);
- return cpustate;
-}
-
-/*****************************************************************************/
-/* Pentium */
-
-
-static CPU_INIT( pentium )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb
- i386_state *cpustate = i386_common_init(96);
- i386_pentium_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( pentium )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x00000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x003f7fd7;
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 5 (Pentium), Model 2 (75 - 200MHz), Stepping 5
- REG32(EAX) = 0;
- REG32(EDX) = (5 << 8) | (2 << 4) | (5);
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x01;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- // [ 2:2] I/O breakpoints
- // [ 4:4] Time Stamp Counter
- // [ 5:5] Pentium CPU style model specific registers
- // [ 7:7] Machine Check Exception
- // [ 8:8] CMPXCHG8B instruction
- cpustate->feature_flags = 0x000001bf;
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-/*****************************************************************************/
-/* Cyrix MediaGX */
-
-
-static CPU_INIT( mediagx )
-{
- // probably 32 unified
- i386_state *cpustate = i386_common_init(32);
- i386_mediagx_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( mediagx )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x00000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 4, Model 4 (MediaGX)
- REG32(EAX) = 0;
- REG32(EDX) = (4 << 8) | (4 << 4) | (1); /* TODO: is this correct? */
-
- cpustate->cpuid_id0 = 0x69727943; // Cyri
- cpustate->cpuid_id1 = 0x736e4978; // xIns
- cpustate->cpuid_id2 = 0x6d616574; // tead
-
- cpustate->cpuid_max_input_value_eax = 0x01;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- cpustate->feature_flags = 0x00000001;
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-/*****************************************************************************/
-/* Intel Pentium Pro */
-
-static CPU_INIT( pentium_pro )
-{
- // 64 dtlb small, 32 itlb
- i386_state *cpustate = i386_common_init(96);
- i386_pentium_pro_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( pentium_pro )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 6, Model 1 (Pentium Pro)
- REG32(EAX) = 0;
- REG32(EDX) = (6 << 8) | (1 << 4) | (1); /* TODO: is this correct? */
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x02;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- // [ 2:2] I/O breakpoints
- // [ 4:4] Time Stamp Counter
- // [ 5:5] Pentium CPU style model specific registers
- // [ 7:7] Machine Check Exception
- // [ 8:8] CMPXCHG8B instruction
- // [15:15] CMOV and FCMOV
- // No MMX
- cpustate->feature_flags = 0x000081bf;
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-/*****************************************************************************/
-/* Intel Pentium MMX */
-
-static CPU_INIT( pentium_mmx )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
- i386_state *cpustate = i386_common_init(96);
- i386_pentium_mmx_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( pentium_mmx )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 5, Model 4 (P55C)
- REG32(EAX) = 0;
- REG32(EDX) = (5 << 8) | (4 << 4) | (1);
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x01;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- // [ 2:2] I/O breakpoints
- // [ 4:4] Time Stamp Counter
- // [ 5:5] Pentium CPU style model specific registers
- // [ 7:7] Machine Check Exception
- // [ 8:8] CMPXCHG8B instruction
- // [23:23] MMX instructions
- cpustate->feature_flags = 0x008001bf;
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-/*****************************************************************************/
-/* Intel Pentium II */
-
-static CPU_INIT( pentium2 )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
- i386_state *cpustate = i386_common_init(96);
- i386_pentium2_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( pentium2 )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 6, Model 3 (Pentium II / Klamath)
- REG32(EAX) = 0;
- REG32(EDX) = (6 << 8) | (3 << 4) | (1); /* TODO: is this correct? */
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x02;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- cpustate->feature_flags = 0x008081bf; // TODO: enable relevant flags here
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-/*****************************************************************************/
-/* Intel Pentium III */
-
-static CPU_INIT( pentium3 )
-{
- // 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
- i386_state *cpustate = i386_common_init(96);
- i386_pentium3_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( pentium3 )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [11:8] Family
- // [ 7:4] Model
- // [ 3:0] Stepping ID
- // Family 6, Model 8 (Pentium III / Coppermine)
- REG32(EAX) = 0;
- REG32(EDX) = (6 << 8) | (8 << 4) | (10);
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x03;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- // [ 4:4] Time Stamp Counter
- // [ D:D] PTE Global Bit
- cpustate->feature_flags = 0x00002011; // TODO: enable relevant flags here
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-/*****************************************************************************/
-/* Intel Pentium 4 */
-
-static CPU_INIT( pentium4 )
-{
- // 128 dtlb, 64 itlb
- i386_state *cpustate = i386_common_init(196);
- i386_pentium4_cpu_init_main(cpustate);
- return cpustate;
-}
-
-static CPU_RESET( pentium4 )
-{
- zero_state(cpustate);
- vtlb_flush_dynamic(cpustate->vtlb);
-
- cpustate->sreg[CS].selector = 0xf000;
- cpustate->sreg[CS].base = 0xffff0000;
- cpustate->sreg[CS].limit = 0xffff;
- cpustate->sreg[CS].flags = 0x009b;
-
- cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
- cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffff;
- cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x0092;
-
- cpustate->idtr.base = 0;
- cpustate->idtr.limit = 0x3ff;
-
- cpustate->a20_mask = ~0;
-
- cpustate->cr[0] = 0x60000010;
- cpustate->eflags = 0x00200000;
- cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
- cpustate->eip = 0xfff0;
- cpustate->mxcsr = 0x1f80;
- cpustate->smm = false;
- cpustate->smi_latched = false;
- cpustate->smbase = 0x30000;
- cpustate->nmi_masked = false;
- cpustate->nmi_latched = false;
-
- x87_reset(cpustate);
-
- // [27:20] Extended family
- // [19:16] Extended model
- // [13:12] Type
- // [11: 8] Family
- // [ 7: 4] Model
- // [ 3: 0] Stepping ID
- // Family 15, Model 0 (Pentium 4 / Willamette)
- REG32(EAX) = 0;
- REG32(EDX) = (0 << 20) | (0xf << 8) | (0 << 4) | (1);
-
- cpustate->cpuid_id0 = 0x756e6547; // Genu
- cpustate->cpuid_id1 = 0x49656e69; // ineI
- cpustate->cpuid_id2 = 0x6c65746e; // ntel
-
- cpustate->cpuid_max_input_value_eax = 0x02;
- cpustate->cpu_version = REG32(EDX);
-
- // [ 0:0] FPU on chip
- cpustate->feature_flags = 0x00000001; // TODO: enable relevant flags here
-
- CHANGE_PC(cpustate,cpustate->eip);
-}
-
-static void pentium_smi(i386_state *cpustate)
-{
- i386_pentium_smi_main(cpustate);
-}
-
-void i386_call_pseudo_bios_int_main(i386_state *cpustate, int interrupt)
-{
-#ifdef I386_PSEUDO_BIOS
- BIOS_INT(interrupt)
-#endif
-}
-
-void i386_call_pseudo_bios_call_main(i386_state *cpustate, UINT16 addr)
-{
-#ifdef I386_PSEUDO_BIOS
- BIOS_CALL(addr);
-#endif
-
-}
}
}
-extern void i386_call_pseudo_bios_call_main(i386_state *cpustate, UINT16 addr);
static void I386OP(call_abs16)(i386_state *cpustate) // Opcode 0x9a
{
UINT16 offset = FETCH16(cpustate);
UINT16 ptr = FETCH16(cpustate);
- i386_call_pseudo_bios_call_main(cpustate, ((ptr << 4) + offset) & cpustate->a20_mask);
+#ifdef I386_PSEUDO_BIOS
+ BIOS_CALL(((ptr << 4) + offset) & cpustate->a20_mask)
+#endif
if( PROTECTED_MODE && !V8086_MODE)
{
{
INT16 disp = FETCH16(cpustate);
- i386_call_pseudo_bios_call_main(cpustate, (cpustate->pc + disp) & cpustate->a20_mask);
+#ifdef I386_PSEUDO_BIOS
+ BIOS_CALL((cpustate->pc + disp) & cpustate->a20_mask)
+#endif
PUSH16(cpustate, cpustate->eip );
if (cpustate->sreg[CS].d)
address = READ16(cpustate,ea);
CYCLES(cpustate,CYCLES_CALL_MEM); /* TODO: Timing = 10 + m */
}
- i386_call_pseudo_bios_call_main(cpustate, ((cpustate->sreg[CS].selector << 4) + address) & cpustate->a20_mask);
+#ifdef I386_PSEUDO_BIOS
+ BIOS_CALL(((cpustate->sreg[CS].selector << 4) + address) & cpustate->a20_mask)
+#endif
PUSH16(cpustate, cpustate->eip );
cpustate->eip = address;
CHANGE_PC(cpustate,cpustate->eip);
address = READ16(cpustate,ea + 0);
selector = READ16(cpustate,ea + 2);
CYCLES(cpustate,CYCLES_CALL_MEM_INTERSEG); /* TODO: Timing = 10 + m */
- i386_call_pseudo_bios_call_main(cpustate, ((selector << 4) + address) & cpustate->a20_mask);
+#ifdef I386_PSEUDO_BIOS
+ BIOS_CALL(((selector << 4) + address) & cpustate->a20_mask)
+#endif
if(PROTECTED_MODE && !V8086_MODE)
{
i386_protected_mode_call(cpustate,selector,address,1,0);
cpustate->ext = 1;
}
-extern void i386_call_pseudo_bios_int_main(i386_state *cpustate, int interrupt);
-
static void I386OP(int)(i386_state *cpustate) // Opcode 0xcd
{
int interrupt = FETCH(cpustate);
CYCLES(cpustate,CYCLES_INT);
- i386_call_pseudo_bios_int_main(cpustate, interrupt);
+#ifdef I386_PSEUDO_BIOS
+ BIOS_INT(interrupt)
+#endif
cpustate->ext = 0; // not an external interrupt
i386_trap(cpustate,interrupt, 1, 0);
cpustate->ext = 1;
#define OP_4BYTE3AF2 0x00400000
#define OP_4BYTE38F3 0x00200000
-extern const X86_OPCODE x86_opcode_table[];
+static const X86_OPCODE x86_opcode_table[] =
+{
+// Opcode Flags 16-bit handler 32-bit handler
+ { 0x00, OP_I386, I386OP(add_rm8_r8), I386OP(add_rm8_r8), true },
+ { 0x01, OP_I386, I386OP(add_rm16_r16), I386OP(add_rm32_r32), true },
+ { 0x02, OP_I386, I386OP(add_r8_rm8), I386OP(add_r8_rm8), false},
+ { 0x03, OP_I386, I386OP(add_r16_rm16), I386OP(add_r32_rm32), false},
+ { 0x04, OP_I386, I386OP(add_al_i8), I386OP(add_al_i8), false},
+ { 0x05, OP_I386, I386OP(add_ax_i16), I386OP(add_eax_i32), false},
+ { 0x06, OP_I386, I386OP(push_es16), I386OP(push_es32), false},
+ { 0x07, OP_I386, I386OP(pop_es16), I386OP(pop_es32), false},
+ { 0x08, OP_I386, I386OP(or_rm8_r8), I386OP(or_rm8_r8), true },
+ { 0x09, OP_I386, I386OP(or_rm16_r16), I386OP(or_rm32_r32), true },
+ { 0x0A, OP_I386, I386OP(or_r8_rm8), I386OP(or_r8_rm8), false},
+ { 0x0B, OP_I386, I386OP(or_r16_rm16), I386OP(or_r32_rm32), false},
+ { 0x0C, OP_I386, I386OP(or_al_i8), I386OP(or_al_i8), false},
+ { 0x0D, OP_I386, I386OP(or_ax_i16), I386OP(or_eax_i32), false},
+ { 0x0E, OP_I386, I386OP(push_cs16), I386OP(push_cs32), false},
+ { 0x0F, OP_I386, I386OP(decode_two_byte), I386OP(decode_two_byte), true },
+ { 0x10, OP_I386, I386OP(adc_rm8_r8), I386OP(adc_rm8_r8), true },
+ { 0x11, OP_I386, I386OP(adc_rm16_r16), I386OP(adc_rm32_r32), true },
+ { 0x12, OP_I386, I386OP(adc_r8_rm8), I386OP(adc_r8_rm8), false},
+ { 0x13, OP_I386, I386OP(adc_r16_rm16), I386OP(adc_r32_rm32), false},
+ { 0x14, OP_I386, I386OP(adc_al_i8), I386OP(adc_al_i8), false},
+ { 0x15, OP_I386, I386OP(adc_ax_i16), I386OP(adc_eax_i32), false},
+ { 0x16, OP_I386, I386OP(push_ss16), I386OP(push_ss32), false},
+ { 0x17, OP_I386, I386OP(pop_ss16), I386OP(pop_ss32), false},
+ { 0x18, OP_I386, I386OP(sbb_rm8_r8), I386OP(sbb_rm8_r8), true },
+ { 0x19, OP_I386, I386OP(sbb_rm16_r16), I386OP(sbb_rm32_r32), true },
+ { 0x1A, OP_I386, I386OP(sbb_r8_rm8), I386OP(sbb_r8_rm8), false},
+ { 0x1B, OP_I386, I386OP(sbb_r16_rm16), I386OP(sbb_r32_rm32), false},
+ { 0x1C, OP_I386, I386OP(sbb_al_i8), I386OP(sbb_al_i8), false},
+ { 0x1D, OP_I386, I386OP(sbb_ax_i16), I386OP(sbb_eax_i32), false},
+ { 0x1E, OP_I386, I386OP(push_ds16), I386OP(push_ds32), false},
+ { 0x1F, OP_I386, I386OP(pop_ds16), I386OP(pop_ds32), false},
+ { 0x20, OP_I386, I386OP(and_rm8_r8), I386OP(and_rm8_r8), true },
+ { 0x21, OP_I386, I386OP(and_rm16_r16), I386OP(and_rm32_r32), true },
+ { 0x22, OP_I386, I386OP(and_r8_rm8), I386OP(and_r8_rm8), false},
+ { 0x23, OP_I386, I386OP(and_r16_rm16), I386OP(and_r32_rm32), false},
+ { 0x24, OP_I386, I386OP(and_al_i8), I386OP(and_al_i8), false},
+ { 0x25, OP_I386, I386OP(and_ax_i16), I386OP(and_eax_i32), false},
+ { 0x26, OP_I386, I386OP(segment_ES), I386OP(segment_ES), false},
+ { 0x27, OP_I386, I386OP(daa), I386OP(daa), false},
+ { 0x28, OP_I386, I386OP(sub_rm8_r8), I386OP(sub_rm8_r8), true },
+ { 0x29, OP_I386, I386OP(sub_rm16_r16), I386OP(sub_rm32_r32), true },
+ { 0x2A, OP_I386, I386OP(sub_r8_rm8), I386OP(sub_r8_rm8), false},
+ { 0x2B, OP_I386, I386OP(sub_r16_rm16), I386OP(sub_r32_rm32), false},
+ { 0x2C, OP_I386, I386OP(sub_al_i8), I386OP(sub_al_i8), false},
+ { 0x2D, OP_I386, I386OP(sub_ax_i16), I386OP(sub_eax_i32), false},
+ { 0x2E, OP_I386, I386OP(segment_CS), I386OP(segment_CS), false},
+ { 0x2F, OP_I386, I386OP(das), I386OP(das), false},
+ { 0x30, OP_I386, I386OP(xor_rm8_r8), I386OP(xor_rm8_r8), true },
+ { 0x31, OP_I386, I386OP(xor_rm16_r16), I386OP(xor_rm32_r32), true },
+ { 0x32, OP_I386, I386OP(xor_r8_rm8), I386OP(xor_r8_rm8), false},
+ { 0x33, OP_I386, I386OP(xor_r16_rm16), I386OP(xor_r32_rm32), false},
+ { 0x34, OP_I386, I386OP(xor_al_i8), I386OP(xor_al_i8), false},
+ { 0x35, OP_I386, I386OP(xor_ax_i16), I386OP(xor_eax_i32), false},
+ { 0x36, OP_I386, I386OP(segment_SS), I386OP(segment_SS), false},
+ { 0x37, OP_I386, I386OP(aaa), I386OP(aaa), false},
+ { 0x38, OP_I386, I386OP(cmp_rm8_r8), I386OP(cmp_rm8_r8), false},
+ { 0x39, OP_I386, I386OP(cmp_rm16_r16), I386OP(cmp_rm32_r32), false},
+ { 0x3A, OP_I386, I386OP(cmp_r8_rm8), I386OP(cmp_r8_rm8), false},
+ { 0x3B, OP_I386, I386OP(cmp_r16_rm16), I386OP(cmp_r32_rm32), false},
+ { 0x3C, OP_I386, I386OP(cmp_al_i8), I386OP(cmp_al_i8), false},
+ { 0x3D, OP_I386, I386OP(cmp_ax_i16), I386OP(cmp_eax_i32), false},
+ { 0x3E, OP_I386, I386OP(segment_DS), I386OP(segment_DS), false},
+ { 0x3F, OP_I386, I386OP(aas), I386OP(aas), false},
+ { 0x40, OP_I386, I386OP(inc_ax), I386OP(inc_eax), false},
+ { 0x41, OP_I386, I386OP(inc_cx), I386OP(inc_ecx), false},
+ { 0x42, OP_I386, I386OP(inc_dx), I386OP(inc_edx), false},
+ { 0x43, OP_I386, I386OP(inc_bx), I386OP(inc_ebx), false},
+ { 0x44, OP_I386, I386OP(inc_sp), I386OP(inc_esp), false},
+ { 0x45, OP_I386, I386OP(inc_bp), I386OP(inc_ebp), false},
+ { 0x46, OP_I386, I386OP(inc_si), I386OP(inc_esi), false},
+ { 0x47, OP_I386, I386OP(inc_di), I386OP(inc_edi), false},
+ { 0x48, OP_I386, I386OP(dec_ax), I386OP(dec_eax), false},
+ { 0x49, OP_I386, I386OP(dec_cx), I386OP(dec_ecx), false},
+ { 0x4A, OP_I386, I386OP(dec_dx), I386OP(dec_edx), false},
+ { 0x4B, OP_I386, I386OP(dec_bx), I386OP(dec_ebx), false},
+ { 0x4C, OP_I386, I386OP(dec_sp), I386OP(dec_esp), false},
+ { 0x4D, OP_I386, I386OP(dec_bp), I386OP(dec_ebp), false},
+ { 0x4E, OP_I386, I386OP(dec_si), I386OP(dec_esi), false},
+ { 0x4F, OP_I386, I386OP(dec_di), I386OP(dec_edi), false},
+ { 0x50, OP_I386, I386OP(push_ax), I386OP(push_eax), false},
+ { 0x51, OP_I386, I386OP(push_cx), I386OP(push_ecx), false},
+ { 0x52, OP_I386, I386OP(push_dx), I386OP(push_edx), false},
+ { 0x53, OP_I386, I386OP(push_bx), I386OP(push_ebx), false},
+ { 0x54, OP_I386, I386OP(push_sp), I386OP(push_esp), false},
+ { 0x55, OP_I386, I386OP(push_bp), I386OP(push_ebp), false},
+ { 0x56, OP_I386, I386OP(push_si), I386OP(push_esi), false},
+ { 0x57, OP_I386, I386OP(push_di), I386OP(push_edi), false},
+ { 0x58, OP_I386, I386OP(pop_ax), I386OP(pop_eax), false},
+ { 0x59, OP_I386, I386OP(pop_cx), I386OP(pop_ecx), false},
+ { 0x5A, OP_I386, I386OP(pop_dx), I386OP(pop_edx), false},
+ { 0x5B, OP_I386, I386OP(pop_bx), I386OP(pop_ebx), false},
+ { 0x5C, OP_I386, I386OP(pop_sp), I386OP(pop_esp), false},
+ { 0x5D, OP_I386, I386OP(pop_bp), I386OP(pop_ebp), false},
+ { 0x5E, OP_I386, I386OP(pop_si), I386OP(pop_esi), false},
+ { 0x5F, OP_I386, I386OP(pop_di), I386OP(pop_edi), false},
+ { 0x60, OP_I386, I386OP(pusha), I386OP(pushad), false},
+ { 0x61, OP_I386, I386OP(popa), I386OP(popad), false},
+ { 0x62, OP_I386, I386OP(bound_r16_m16_m16), I386OP(bound_r32_m32_m32), false},
+ { 0x63, OP_I386, I386OP(arpl), I386OP(arpl), false},
+ { 0x64, OP_I386, I386OP(segment_FS), I386OP(segment_FS), false},
+ { 0x65, OP_I386, I386OP(segment_GS), I386OP(segment_GS), false},
+ { 0x66, OP_I386, I386OP(operand_size), I386OP(operand_size), false},
+ { 0x67, OP_I386, I386OP(address_size), I386OP(address_size), false},
+ { 0x68, OP_I386, I386OP(push_i16), I386OP(push_i32), false},
+ { 0x69, OP_I386, I386OP(imul_r16_rm16_i16), I386OP(imul_r32_rm32_i32), false},
+ { 0x6A, OP_I386, I386OP(push_i8), I386OP(push_i8), false},
+ { 0x6B, OP_I386, I386OP(imul_r16_rm16_i8), I386OP(imul_r32_rm32_i8), false},
+ { 0x6C, OP_I386, I386OP(insb), I386OP(insb), false},
+ { 0x6D, OP_I386, I386OP(insw), I386OP(insd), false},
+ { 0x6E, OP_I386, I386OP(outsb), I386OP(outsb), false},
+ { 0x6F, OP_I386, I386OP(outsw), I386OP(outsd), false},
+ { 0x70, OP_I386, I386OP(jo_rel8), I386OP(jo_rel8), false},
+ { 0x71, OP_I386, I386OP(jno_rel8), I386OP(jno_rel8), false},
+ { 0x72, OP_I386, I386OP(jc_rel8), I386OP(jc_rel8), false},
+ { 0x73, OP_I386, I386OP(jnc_rel8), I386OP(jnc_rel8), false},
+ { 0x74, OP_I386, I386OP(jz_rel8), I386OP(jz_rel8), false},
+ { 0x75, OP_I386, I386OP(jnz_rel8), I386OP(jnz_rel8), false},
+ { 0x76, OP_I386, I386OP(jbe_rel8), I386OP(jbe_rel8), false},
+ { 0x77, OP_I386, I386OP(ja_rel8), I386OP(ja_rel8), false},
+ { 0x78, OP_I386, I386OP(js_rel8), I386OP(js_rel8), false},
+ { 0x79, OP_I386, I386OP(jns_rel8), I386OP(jns_rel8), false},
+ { 0x7A, OP_I386, I386OP(jp_rel8), I386OP(jp_rel8), false},
+ { 0x7B, OP_I386, I386OP(jnp_rel8), I386OP(jnp_rel8), false},
+ { 0x7C, OP_I386, I386OP(jl_rel8), I386OP(jl_rel8), false},
+ { 0x7D, OP_I386, I386OP(jge_rel8), I386OP(jge_rel8), false},
+ { 0x7E, OP_I386, I386OP(jle_rel8), I386OP(jle_rel8), false},
+ { 0x7F, OP_I386, I386OP(jg_rel8), I386OP(jg_rel8), false},
+ { 0x80, OP_I386, I386OP(group80_8), I386OP(group80_8), true },
+ { 0x81, OP_I386, I386OP(group81_16), I386OP(group81_32), true },
+ { 0x82, OP_I386, I386OP(group80_8), I386OP(group80_8), true },
+ { 0x83, OP_I386, I386OP(group83_16), I386OP(group83_32), true },
+ { 0x84, OP_I386, I386OP(test_rm8_r8), I386OP(test_rm8_r8), false},
+ { 0x85, OP_I386, I386OP(test_rm16_r16), I386OP(test_rm32_r32), false},
+ { 0x86, OP_I386, I386OP(xchg_r8_rm8), I386OP(xchg_r8_rm8), true },
+ { 0x87, OP_I386, I386OP(xchg_r16_rm16), I386OP(xchg_r32_rm32), true },
+ { 0x88, OP_I386, I386OP(mov_rm8_r8), I386OP(mov_rm8_r8), false},
+ { 0x89, OP_I386, I386OP(mov_rm16_r16), I386OP(mov_rm32_r32), false},
+ { 0x8A, OP_I386, I386OP(mov_r8_rm8), I386OP(mov_r8_rm8), false},
+ { 0x8B, OP_I386, I386OP(mov_r16_rm16), I386OP(mov_r32_rm32), false},
+ { 0x8C, OP_I386, I386OP(mov_rm16_sreg), I386OP(mov_rm16_sreg), false},
+ { 0x8D, OP_I386, I386OP(lea16), I386OP(lea32), false},
+ { 0x8E, OP_I386, I386OP(mov_sreg_rm16), I386OP(mov_sreg_rm16), false},
+ { 0x8F, OP_I386, I386OP(pop_rm16), I386OP(pop_rm32), false},
+ { 0x90, OP_I386, I386OP(nop), I386OP(nop), false},
+ { 0x91, OP_I386, I386OP(xchg_ax_cx), I386OP(xchg_eax_ecx), false},
+ { 0x92, OP_I386, I386OP(xchg_ax_dx), I386OP(xchg_eax_edx), false},
+ { 0x93, OP_I386, I386OP(xchg_ax_bx), I386OP(xchg_eax_ebx), false},
+ { 0x94, OP_I386, I386OP(xchg_ax_sp), I386OP(xchg_eax_esp), false},
+ { 0x95, OP_I386, I386OP(xchg_ax_bp), I386OP(xchg_eax_ebp), false},
+ { 0x96, OP_I386, I386OP(xchg_ax_si), I386OP(xchg_eax_esi), false},
+ { 0x97, OP_I386, I386OP(xchg_ax_di), I386OP(xchg_eax_edi), false},
+ { 0x98, OP_I386, I386OP(cbw), I386OP(cwde), false},
+ { 0x99, OP_I386, I386OP(cwd), I386OP(cdq), false},
+ { 0x9A, OP_I386, I386OP(call_abs16), I386OP(call_abs32), false},
+ { 0x9B, OP_I386, I386OP(wait), I386OP(wait), false},
+ { 0x9C, OP_I386, I386OP(pushf), I386OP(pushfd), false},
+ { 0x9D, OP_I386, I386OP(popf), I386OP(popfd), false},
+ { 0x9E, OP_I386, I386OP(sahf), I386OP(sahf), false},
+ { 0x9F, OP_I386, I386OP(lahf), I386OP(lahf), false},
+ { 0xA0, OP_I386, I386OP(mov_al_m8), I386OP(mov_al_m8), false},
+ { 0xA1, OP_I386, I386OP(mov_ax_m16), I386OP(mov_eax_m32), false},
+ { 0xA2, OP_I386, I386OP(mov_m8_al), I386OP(mov_m8_al), false},
+ { 0xA3, OP_I386, I386OP(mov_m16_ax), I386OP(mov_m32_eax), false},
+ { 0xA4, OP_I386, I386OP(movsb), I386OP(movsb), false},
+ { 0xA5, OP_I386, I386OP(movsw), I386OP(movsd), false},
+ { 0xA6, OP_I386, I386OP(cmpsb), I386OP(cmpsb), false},
+ { 0xA7, OP_I386, I386OP(cmpsw), I386OP(cmpsd), false},
+ { 0xA8, OP_I386, I386OP(test_al_i8), I386OP(test_al_i8), false},
+ { 0xA9, OP_I386, I386OP(test_ax_i16), I386OP(test_eax_i32), false},
+ { 0xAA, OP_I386, I386OP(stosb), I386OP(stosb), false},
+ { 0xAB, OP_I386, I386OP(stosw), I386OP(stosd), false},
+ { 0xAC, OP_I386, I386OP(lodsb), I386OP(lodsb), false},
+ { 0xAD, OP_I386, I386OP(lodsw), I386OP(lodsd), false},
+ { 0xAE, OP_I386, I386OP(scasb), I386OP(scasb), false},
+ { 0xAF, OP_I386, I386OP(scasw), I386OP(scasd), false},
+ { 0xB0, OP_I386, I386OP(mov_al_i8), I386OP(mov_al_i8), false},
+ { 0xB1, OP_I386, I386OP(mov_cl_i8), I386OP(mov_cl_i8), false},
+ { 0xB2, OP_I386, I386OP(mov_dl_i8), I386OP(mov_dl_i8), false},
+ { 0xB3, OP_I386, I386OP(mov_bl_i8), I386OP(mov_bl_i8), false},
+ { 0xB4, OP_I386, I386OP(mov_ah_i8), I386OP(mov_ah_i8), false},
+ { 0xB5, OP_I386, I386OP(mov_ch_i8), I386OP(mov_ch_i8), false},
+ { 0xB6, OP_I386, I386OP(mov_dh_i8), I386OP(mov_dh_i8), false},
+ { 0xB7, OP_I386, I386OP(mov_bh_i8), I386OP(mov_bh_i8), false},
+ { 0xB8, OP_I386, I386OP(mov_ax_i16), I386OP(mov_eax_i32), false},
+ { 0xB9, OP_I386, I386OP(mov_cx_i16), I386OP(mov_ecx_i32), false},
+ { 0xBA, OP_I386, I386OP(mov_dx_i16), I386OP(mov_edx_i32), false},
+ { 0xBB, OP_I386, I386OP(mov_bx_i16), I386OP(mov_ebx_i32), false},
+ { 0xBC, OP_I386, I386OP(mov_sp_i16), I386OP(mov_esp_i32), false},
+ { 0xBD, OP_I386, I386OP(mov_bp_i16), I386OP(mov_ebp_i32), false},
+ { 0xBE, OP_I386, I386OP(mov_si_i16), I386OP(mov_esi_i32), false},
+ { 0xBF, OP_I386, I386OP(mov_di_i16), I386OP(mov_edi_i32), false},
+ { 0xC0, OP_I386, I386OP(groupC0_8), I386OP(groupC0_8), false},
+ { 0xC1, OP_I386, I386OP(groupC1_16), I386OP(groupC1_32), false},
+ { 0xC2, OP_I386, I386OP(ret_near16_i16), I386OP(ret_near32_i16), false},
+ { 0xC3, OP_I386, I386OP(ret_near16), I386OP(ret_near32), false},
+ { 0xC4, OP_I386, I386OP(les16), I386OP(les32), false},
+ { 0xC5, OP_I386, I386OP(lds16), I386OP(lds32), false},
+ { 0xC6, OP_I386, I386OP(mov_rm8_i8), I386OP(mov_rm8_i8), false},
+ { 0xC7, OP_I386, I386OP(mov_rm16_i16), I386OP(mov_rm32_i32), false},
+ { 0xC8, OP_I386, I386OP(enter16), I386OP(enter32), false},
+ { 0xC9, OP_I386, I386OP(leave16), I386OP(leave32), false},
+ { 0xCA, OP_I386, I386OP(retf_i16), I386OP(retf_i32), false},
+ { 0xCB, OP_I386, I386OP(retf16), I386OP(retf32), false},
+ { 0xCC, OP_I386, I386OP(int3), I386OP(int3), false},
+ { 0xCD, OP_I386, I386OP(int), I386OP(int), false},
+ { 0xCE, OP_I386, I386OP(into), I386OP(into), false},
+ { 0xCF, OP_I386, I386OP(iret16), I386OP(iret32), false},
+ { 0xD0, OP_I386, I386OP(groupD0_8), I386OP(groupD0_8), false},
+ { 0xD1, OP_I386, I386OP(groupD1_16), I386OP(groupD1_32), false},
+ { 0xD2, OP_I386, I386OP(groupD2_8), I386OP(groupD2_8), false},
+ { 0xD3, OP_I386, I386OP(groupD3_16), I386OP(groupD3_32), false},
+ { 0xD4, OP_I386, I386OP(aam), I386OP(aam), false},
+ { 0xD5, OP_I386, I386OP(aad), I386OP(aad), false},
+ { 0xD6, OP_I386, I386OP(setalc), I386OP(setalc), false},
+ { 0xD7, OP_I386, I386OP(xlat), I386OP(xlat), false},
+ { 0xD8, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xD9, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xDA, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xDB, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xDC, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xDD, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xDE, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xDF, OP_I386, I386OP(escape), I386OP(escape), false},
+ { 0xD8, OP_FPU, I386OP(x87_group_d8), I386OP(x87_group_d8), false},
+ { 0xD9, OP_FPU, I386OP(x87_group_d9), I386OP(x87_group_d9), false},
+ { 0xDA, OP_FPU, I386OP(x87_group_da), I386OP(x87_group_da), false},
+ { 0xDB, OP_FPU, I386OP(x87_group_db), I386OP(x87_group_db), false},
+ { 0xDC, OP_FPU, I386OP(x87_group_dc), I386OP(x87_group_dc), false},
+ { 0xDD, OP_FPU, I386OP(x87_group_dd), I386OP(x87_group_dd), false},
+ { 0xDE, OP_FPU, I386OP(x87_group_de), I386OP(x87_group_de), false},
+ { 0xDF, OP_FPU, I386OP(x87_group_df), I386OP(x87_group_df), false},
+ { 0xE0, OP_I386, I386OP(loopne16), I386OP(loopne32), false},
+ { 0xE1, OP_I386, I386OP(loopz16), I386OP(loopz32), false},
+ { 0xE2, OP_I386, I386OP(loop16), I386OP(loop32), false},
+ { 0xE3, OP_I386, I386OP(jcxz16), I386OP(jcxz32), false},
+ { 0xE4, OP_I386, I386OP(in_al_i8), I386OP(in_al_i8), false},
+ { 0xE5, OP_I386, I386OP(in_ax_i8), I386OP(in_eax_i8), false},
+ { 0xE6, OP_I386, I386OP(out_al_i8), I386OP(out_al_i8), false},
+ { 0xE7, OP_I386, I386OP(out_ax_i8), I386OP(out_eax_i8), false},
+ { 0xE8, OP_I386, I386OP(call_rel16), I386OP(call_rel32), false},
+ { 0xE9, OP_I386, I386OP(jmp_rel16), I386OP(jmp_rel32), false},
+ { 0xEA, OP_I386, I386OP(jmp_abs16), I386OP(jmp_abs32), false},
+ { 0xEB, OP_I386, I386OP(jmp_rel8), I386OP(jmp_rel8), false},
+ { 0xEC, OP_I386, I386OP(in_al_dx), I386OP(in_al_dx), false},
+ { 0xED, OP_I386, I386OP(in_ax_dx), I386OP(in_eax_dx), false},
+ { 0xEE, OP_I386, I386OP(out_al_dx), I386OP(out_al_dx), false},
+ { 0xEF, OP_I386, I386OP(out_ax_dx), I386OP(out_eax_dx), false},
+ { 0xF0, OP_I386, I386OP(lock), I386OP(lock), false},
+ { 0xF1, OP_I386, I386OP(invalid), I386OP(invalid), false},
+ { 0xF2, OP_I386, I386OP(repne), I386OP(repne), false},
+ { 0xF3, OP_I386, I386OP(rep), I386OP(rep), false},
+ { 0xF4, OP_I386, I386OP(hlt), I386OP(hlt), false},
+ { 0xF5, OP_I386, I386OP(cmc), I386OP(cmc), false},
+ { 0xF6, OP_I386, I386OP(groupF6_8), I386OP(groupF6_8), true },
+ { 0xF7, OP_I386, I386OP(groupF7_16), I386OP(groupF7_32), true },
+ { 0xF8, OP_I386, I386OP(clc), I386OP(clc), false},
+ { 0xF9, OP_I386, I386OP(stc), I386OP(stc), false},
+ { 0xFA, OP_I386, I386OP(cli), I386OP(cli), false},
+ { 0xFB, OP_I386, I386OP(sti), I386OP(sti), false},
+ { 0xFC, OP_I386, I386OP(cld), I386OP(cld), false},
+ { 0xFD, OP_I386, I386OP(std), I386OP(std), false},
+ { 0xFE, OP_I386, I386OP(groupFE_8), I386OP(groupFE_8), true },
+ { 0xFF, OP_I386, I386OP(groupFF_16), I386OP(groupFF_32), true },
+ /* 0F ?? */
+ { 0x00, OP_2BYTE|OP_I386, I386OP(group0F00_16), I386OP(group0F00_32), false},
+ { 0x01, OP_2BYTE|OP_I386, I386OP(group0F01_16), I386OP(group0F01_32), false},
+ { 0x01, OP_2BYTE|OP_I486, I486OP(group0F01_16), I486OP(group0F01_32), false},
+ { 0x02, OP_2BYTE|OP_I386, I386OP(lar_r16_rm16), I386OP(lar_r32_rm32), false},
+ { 0x03, OP_2BYTE|OP_I386, I386OP(lsl_r16_rm16), I386OP(lsl_r32_rm32), false},
+ { 0x06, OP_2BYTE|OP_I386, I386OP(clts), I386OP(clts), false},
+ { 0x07, OP_2BYTE|OP_I386, I386OP(loadall), I386OP(loadall), false},
+ { 0x08, OP_2BYTE|OP_I486, I486OP(invd), I486OP(invd), false},
+ { 0x09, OP_2BYTE|OP_I486, I486OP(wbinvd), I486OP(wbinvd), false},
+ { 0x0B, OP_2BYTE|OP_PENTIUM, PENTIUMOP(ud2), PENTIUMOP(ud2), false},
+ { 0x10, OP_2BYTE|OP_SSE, SSEOP(movups_r128_rm128), SSEOP(movups_r128_rm128), false},
+ { 0x11, OP_2BYTE|OP_SSE, SSEOP(movups_rm128_r128), SSEOP(movups_rm128_r128), false},
+ { 0x12, OP_2BYTE|OP_SSE, SSEOP(movlps_r128_m64), SSEOP(movlps_r128_m64), false},
+ { 0x13, OP_2BYTE|OP_SSE, SSEOP(movlps_m64_r128), SSEOP(movlps_m64_r128), false},
+ { 0x14, OP_2BYTE|OP_SSE, SSEOP(unpcklps_r128_rm128), SSEOP(unpcklps_r128_rm128), false},
+ { 0x15, OP_2BYTE|OP_SSE, SSEOP(unpckhps_r128_rm128), SSEOP(unpckhps_r128_rm128), false},
+ { 0x16, OP_2BYTE|OP_SSE, SSEOP(movhps_r128_m64), SSEOP(movhps_r128_m64), false},
+ { 0x17, OP_2BYTE|OP_SSE, SSEOP(movhps_m64_r128), SSEOP(movhps_m64_r128), false},
+ { 0x18, OP_2BYTE|OP_PENTIUM, PENTIUMOP(prefetch_m8), PENTIUMOP(prefetch_m8), false},
+ { 0x20, OP_2BYTE|OP_I386, I386OP(mov_r32_cr), I386OP(mov_r32_cr), false},
+ { 0x21, OP_2BYTE|OP_I386, I386OP(mov_r32_dr), I386OP(mov_r32_dr), false},
+ { 0x22, OP_2BYTE|OP_I386, I386OP(mov_cr_r32), I386OP(mov_cr_r32), false},
+ { 0x22, OP_2BYTE|OP_I486, I486OP(mov_cr_r32), I486OP(mov_cr_r32), false},
+ { 0x23, OP_2BYTE|OP_I386, I386OP(mov_dr_r32), I386OP(mov_dr_r32), false},
+ { 0x24, OP_2BYTE|OP_I386, I386OP(mov_r32_tr), I386OP(mov_r32_tr), false},
+ { 0x26, OP_2BYTE|OP_I386, I386OP(mov_tr_r32), I386OP(mov_tr_r32), false},
+ { 0x28, OP_2BYTE|OP_SSE, SSEOP(movaps_r128_rm128), SSEOP(movaps_r128_rm128), false},
+ { 0x29, OP_2BYTE|OP_SSE, SSEOP(movaps_rm128_r128), SSEOP(movaps_rm128_r128), false},
+ { 0x2a, OP_2BYTE|OP_SSE, SSEOP(cvtpi2ps_r128_rm64), SSEOP(cvtpi2ps_r128_rm64), false},
+ { 0x2b, OP_2BYTE|OP_SSE, SSEOP(movntps_m128_r128), SSEOP(movntps_m128_r128), false},
+ { 0x2c, OP_2BYTE|OP_SSE, SSEOP(cvttps2pi_r64_r128m64), SSEOP(cvttps2pi_r64_r128m64),false},
+ { 0x2d, OP_2BYTE|OP_SSE, SSEOP(cvtps2pi_r64_r128m64), SSEOP(cvtps2pi_r64_r128m64),false},
+ { 0x2e, OP_2BYTE|OP_SSE, SSEOP(ucomiss_r128_r128m32), SSEOP(ucomiss_r128_r128m32),false},
+ { 0x2f, OP_2BYTE|OP_SSE, SSEOP(comiss_r128_r128m32), SSEOP(comiss_r128_r128m32), false},
+ { 0x30, OP_2BYTE|OP_PENTIUM, PENTIUMOP(wrmsr), PENTIUMOP(wrmsr), false},
+ { 0x31, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdtsc), PENTIUMOP(rdtsc), false},
+ { 0x32, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdmsr), PENTIUMOP(rdmsr), false},
+ { 0x38, OP_2BYTE|OP_PENTIUM, I386OP(decode_three_byte38), I386OP(decode_three_byte38),false},
+ { 0x3A, OP_2BYTE|OP_PENTIUM, I386OP(decode_three_byte3a), I386OP(decode_three_byte3a),false},
+ { 0x3A, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
+ { 0x3B, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
+ { 0x3C, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
+ { 0x3D, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
+ { 0x40, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovo_r16_rm16), PENTIUMOP(cmovo_r32_rm32), false},
+ { 0x41, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovno_r16_rm16), PENTIUMOP(cmovno_r32_rm32), false},
+ { 0x42, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovb_r16_rm16), PENTIUMOP(cmovb_r32_rm32), false},
+ { 0x43, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovae_r16_rm16), PENTIUMOP(cmovae_r32_rm32), false},
+ { 0x44, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmove_r16_rm16), PENTIUMOP(cmove_r32_rm32), false},
+ { 0x45, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovne_r16_rm16), PENTIUMOP(cmovne_r32_rm32), false},
+ { 0x46, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovbe_r16_rm16), PENTIUMOP(cmovbe_r32_rm32), false},
+ { 0x47, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmova_r16_rm16), PENTIUMOP(cmova_r32_rm32), false},
+ { 0x48, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovs_r16_rm16), PENTIUMOP(cmovs_r32_rm32), false},
+ { 0x49, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovns_r16_rm16), PENTIUMOP(cmovns_r32_rm32), false},
+ { 0x4a, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovp_r16_rm16), PENTIUMOP(cmovp_r32_rm32), false},
+ { 0x4b, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovnp_r16_rm16), PENTIUMOP(cmovnp_r32_rm32), false},
+ { 0x4c, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovl_r16_rm16), PENTIUMOP(cmovl_r32_rm32), false},
+ { 0x4d, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovge_r16_rm16), PENTIUMOP(cmovge_r32_rm32), false},
+ { 0x4e, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovle_r16_rm16), PENTIUMOP(cmovle_r32_rm32), false},
+ { 0x4f, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovg_r16_rm16), PENTIUMOP(cmovg_r32_rm32), false},
+ { 0x50, OP_2BYTE|OP_SSE, SSEOP(movmskps_r16_r128), SSEOP(movmskps_r32_r128), false},
+ { 0x51, OP_2BYTE|OP_SSE, SSEOP(sqrtps_r128_rm128), SSEOP(sqrtps_r128_rm128), false},
+ { 0x52, OP_2BYTE|OP_SSE, SSEOP(rsqrtps_r128_rm128), SSEOP(rsqrtps_r128_rm128), false},
+ { 0x53, OP_2BYTE|OP_SSE, SSEOP(rcpps_r128_rm128), SSEOP(rcpps_r128_rm128), false},
+ { 0x54, OP_2BYTE|OP_SSE, SSEOP(andps_r128_rm128), SSEOP(andps_r128_rm128), false},
+ { 0x55, OP_2BYTE|OP_SSE, SSEOP(andnps_r128_rm128), SSEOP(andnps_r128_rm128), false},
+ { 0x56, OP_2BYTE|OP_SSE, SSEOP(orps_r128_rm128), SSEOP(orps_r128_rm128), false},
+ { 0x57, OP_2BYTE|OP_SSE, SSEOP(xorps), SSEOP(xorps), false},
+ { 0x58, OP_2BYTE|OP_SSE, SSEOP(addps), SSEOP(addps), false},
+ { 0x59, OP_2BYTE|OP_SSE, SSEOP(mulps), SSEOP(mulps), false},
+ { 0x5a, OP_2BYTE|OP_SSE, SSEOP(cvtps2pd_r128_r128m64), SSEOP(cvtps2pd_r128_r128m64),false},
+ { 0x5b, OP_2BYTE|OP_SSE, SSEOP(cvtdq2ps_r128_rm128), SSEOP(cvtdq2ps_r128_rm128), false},
+ { 0x5c, OP_2BYTE|OP_SSE, SSEOP(subps), SSEOP(subps), false},
+ { 0x5d, OP_2BYTE|OP_SSE, SSEOP(minps), SSEOP(minps), false},
+ { 0x5e, OP_2BYTE|OP_SSE, SSEOP(divps), SSEOP(divps), false},
+ { 0x5f, OP_2BYTE|OP_SSE, SSEOP(maxps), SSEOP(maxps), false},
+ { 0x60, OP_2BYTE|OP_MMX, MMXOP(punpcklbw_r64_r64m32), MMXOP(punpcklbw_r64_r64m32),false},
+ { 0x61, OP_2BYTE|OP_MMX, MMXOP(punpcklwd_r64_r64m32), MMXOP(punpcklwd_r64_r64m32),false},
+ { 0x62, OP_2BYTE|OP_MMX, MMXOP(punpckldq_r64_r64m32), MMXOP(punpckldq_r64_r64m32),false},
+ { 0x63, OP_2BYTE|OP_MMX, MMXOP(packsswb_r64_rm64), MMXOP(packsswb_r64_rm64), false},
+ { 0x64, OP_2BYTE|OP_MMX, MMXOP(pcmpgtb_r64_rm64), MMXOP(pcmpgtb_r64_rm64), false},
+ { 0x65, OP_2BYTE|OP_MMX, MMXOP(pcmpgtw_r64_rm64), MMXOP(pcmpgtw_r64_rm64), false},
+ { 0x66, OP_2BYTE|OP_MMX, MMXOP(pcmpgtd_r64_rm64), MMXOP(pcmpgtd_r64_rm64), false},
+ { 0x67, OP_2BYTE|OP_MMX, MMXOP(packuswb_r64_rm64), MMXOP(packuswb_r64_rm64), false},
+ { 0x68, OP_2BYTE|OP_MMX, MMXOP(punpckhbw_r64_rm64), MMXOP(punpckhbw_r64_rm64), false},
+ { 0x69, OP_2BYTE|OP_MMX, MMXOP(punpckhwd_r64_rm64), MMXOP(punpckhwd_r64_rm64), false},
+ { 0x6a, OP_2BYTE|OP_MMX, MMXOP(punpckhdq_r64_rm64), MMXOP(punpckhdq_r64_rm64), false},
+ { 0x6b, OP_2BYTE|OP_MMX, MMXOP(packssdw_r64_rm64), MMXOP(packssdw_r64_rm64), false},
+ { 0x6e, OP_2BYTE|OP_MMX, MMXOP(movd_r64_rm32), MMXOP(movd_r64_rm32), false},
+ { 0x6f, OP_2BYTE|OP_MMX, MMXOP(movq_r64_rm64), MMXOP(movq_r64_rm64), false},
+ { 0x70, OP_2BYTE|OP_MMX, MMXOP(pshufw_r64_rm64_i8), MMXOP(pshufw_r64_rm64_i8), false},
+ { 0x71, OP_2BYTE|OP_MMX, MMXOP(group_0f71), MMXOP(group_0f71), false},
+ { 0x72, OP_2BYTE|OP_MMX, MMXOP(group_0f72), MMXOP(group_0f72), false},
+ { 0x73, OP_2BYTE|OP_MMX, MMXOP(group_0f73), MMXOP(group_0f73), false},
+ { 0x74, OP_2BYTE|OP_CYRIX, I386OP(cyrix_unknown), I386OP(cyrix_unknown), false},
+ { 0x74, OP_2BYTE|OP_MMX, MMXOP(pcmpeqb_r64_rm64), MMXOP(pcmpeqb_r64_rm64), false},
+ { 0x75, OP_2BYTE|OP_MMX, MMXOP(pcmpeqw_r64_rm64), MMXOP(pcmpeqw_r64_rm64), false},
+ { 0x76, OP_2BYTE|OP_MMX, MMXOP(pcmpeqd_r64_rm64), MMXOP(pcmpeqd_r64_rm64), false},
+ { 0x77, OP_2BYTE|OP_MMX, MMXOP(emms), MMXOP(emms), false},
+ { 0x78, OP_2BYTE|OP_CYRIX, I386OP(cyrix_svdc), I386OP(cyrix_svdc), false},
+ { 0x79, OP_2BYTE|OP_CYRIX, I386OP(cyrix_rsdc), I386OP(cyrix_rsdc), false},
+ { 0x7a, OP_2BYTE|OP_CYRIX, I386OP(cyrix_svldt), I386OP(cyrix_svldt), false},
+ { 0x7b, OP_2BYTE|OP_CYRIX, I386OP(cyrix_rsldt), I386OP(cyrix_rsldt), false},
+ { 0x7c, OP_2BYTE|OP_CYRIX, I386OP(cyrix_svts), I386OP(cyrix_svts), false},
+ { 0x7d, OP_2BYTE|OP_CYRIX, I386OP(cyrix_rsts), I386OP(cyrix_rsts), false},
+ { 0x7e, OP_2BYTE|OP_MMX, MMXOP(movd_rm32_r64), MMXOP(movd_rm32_r64), false},
+ { 0x7f, OP_2BYTE|OP_MMX, MMXOP(movq_rm64_r64), MMXOP(movq_rm64_r64), false},
+ { 0x80, OP_2BYTE|OP_I386, I386OP(jo_rel16), I386OP(jo_rel32), false},
+ { 0x81, OP_2BYTE|OP_I386, I386OP(jno_rel16), I386OP(jno_rel32), false},
+ { 0x82, OP_2BYTE|OP_I386, I386OP(jc_rel16), I386OP(jc_rel32), false},
+ { 0x83, OP_2BYTE|OP_I386, I386OP(jnc_rel16), I386OP(jnc_rel32), false},
+ { 0x84, OP_2BYTE|OP_I386, I386OP(jz_rel16), I386OP(jz_rel32), false},
+ { 0x85, OP_2BYTE|OP_I386, I386OP(jnz_rel16), I386OP(jnz_rel32), false},
+ { 0x86, OP_2BYTE|OP_I386, I386OP(jbe_rel16), I386OP(jbe_rel32), false},
+ { 0x87, OP_2BYTE|OP_I386, I386OP(ja_rel16), I386OP(ja_rel32), false},
+ { 0x88, OP_2BYTE|OP_I386, I386OP(js_rel16), I386OP(js_rel32), false},
+ { 0x89, OP_2BYTE|OP_I386, I386OP(jns_rel16), I386OP(jns_rel32), false},
+ { 0x8A, OP_2BYTE|OP_I386, I386OP(jp_rel16), I386OP(jp_rel32), false},
+ { 0x8B, OP_2BYTE|OP_I386, I386OP(jnp_rel16), I386OP(jnp_rel32), false},
+ { 0x8C, OP_2BYTE|OP_I386, I386OP(jl_rel16), I386OP(jl_rel32), false},
+ { 0x8D, OP_2BYTE|OP_I386, I386OP(jge_rel16), I386OP(jge_rel32), false},
+ { 0x8E, OP_2BYTE|OP_I386, I386OP(jle_rel16), I386OP(jle_rel32), false},
+ { 0x8F, OP_2BYTE|OP_I386, I386OP(jg_rel16), I386OP(jg_rel32), false},
+ { 0x90, OP_2BYTE|OP_I386, I386OP(seto_rm8), I386OP(seto_rm8), false},
+ { 0x91, OP_2BYTE|OP_I386, I386OP(setno_rm8), I386OP(setno_rm8), false},
+ { 0x92, OP_2BYTE|OP_I386, I386OP(setc_rm8), I386OP(setc_rm8), false},
+ { 0x93, OP_2BYTE|OP_I386, I386OP(setnc_rm8), I386OP(setnc_rm8), false},
+ { 0x94, OP_2BYTE|OP_I386, I386OP(setz_rm8), I386OP(setz_rm8), false},
+ { 0x95, OP_2BYTE|OP_I386, I386OP(setnz_rm8), I386OP(setnz_rm8), false},
+ { 0x96, OP_2BYTE|OP_I386, I386OP(setbe_rm8), I386OP(setbe_rm8), false},
+ { 0x97, OP_2BYTE|OP_I386, I386OP(seta_rm8), I386OP(seta_rm8), false},
+ { 0x98, OP_2BYTE|OP_I386, I386OP(sets_rm8), I386OP(sets_rm8), false},
+ { 0x99, OP_2BYTE|OP_I386, I386OP(setns_rm8), I386OP(setns_rm8), false},
+ { 0x9A, OP_2BYTE|OP_I386, I386OP(setp_rm8), I386OP(setp_rm8), false},
+ { 0x9B, OP_2BYTE|OP_I386, I386OP(setnp_rm8), I386OP(setnp_rm8), false},
+ { 0x9C, OP_2BYTE|OP_I386, I386OP(setl_rm8), I386OP(setl_rm8), false},
+ { 0x9D, OP_2BYTE|OP_I386, I386OP(setge_rm8), I386OP(setge_rm8), false},
+ { 0x9E, OP_2BYTE|OP_I386, I386OP(setle_rm8), I386OP(setle_rm8), false},
+ { 0x9F, OP_2BYTE|OP_I386, I386OP(setg_rm8), I386OP(setg_rm8), false},
+ { 0xA0, OP_2BYTE|OP_I386, I386OP(push_fs16), I386OP(push_fs32), false},
+ { 0xA1, OP_2BYTE|OP_I386, I386OP(pop_fs16), I386OP(pop_fs32), false},
+ { 0xA2, OP_2BYTE|OP_I486, I486OP(cpuid), I486OP(cpuid), false},
+ { 0xA3, OP_2BYTE|OP_I386, I386OP(bt_rm16_r16), I386OP(bt_rm32_r32), false},
+ { 0xA4, OP_2BYTE|OP_I386, I386OP(shld16_i8), I386OP(shld32_i8), false},
+ { 0xA5, OP_2BYTE|OP_I386, I386OP(shld16_cl), I386OP(shld32_cl), false},
+ { 0xA8, OP_2BYTE|OP_I386, I386OP(push_gs16), I386OP(push_gs32), false},
+ { 0xA9, OP_2BYTE|OP_I386, I386OP(pop_gs16), I386OP(pop_gs32), false},
+ { 0xAA, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rsm), PENTIUMOP(rsm), false},
+ { 0xAB, OP_2BYTE|OP_I386, I386OP(bts_rm16_r16), I386OP(bts_rm32_r32), true },
+ { 0xAC, OP_2BYTE|OP_I386, I386OP(shrd16_i8), I386OP(shrd32_i8), false},
+ { 0xAD, OP_2BYTE|OP_I386, I386OP(shrd16_cl), I386OP(shrd32_cl), false},
+ { 0xAE, OP_2BYTE|OP_SSE, SSEOP(group_0fae), SSEOP(group_0fae), false},
+ { 0xAF, OP_2BYTE|OP_I386, I386OP(imul_r16_rm16), I386OP(imul_r32_rm32), false},
+ { 0xB0, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm8_r8), I486OP(cmpxchg_rm8_r8), true },
+ { 0xB1, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm16_r16), I486OP(cmpxchg_rm32_r32), true },
+ { 0xB2, OP_2BYTE|OP_I386, I386OP(lss16), I386OP(lss32), false},
+ { 0xB3, OP_2BYTE|OP_I386, I386OP(btr_rm16_r16), I386OP(btr_rm32_r32), true },
+ { 0xB4, OP_2BYTE|OP_I386, I386OP(lfs16), I386OP(lfs32), false},
+ { 0xB5, OP_2BYTE|OP_I386, I386OP(lgs16), I386OP(lgs32), false},
+ { 0xB6, OP_2BYTE|OP_I386, I386OP(movzx_r16_rm8), I386OP(movzx_r32_rm8), false},
+ { 0xB7, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movzx_r32_rm16), false},
+ { 0xBA, OP_2BYTE|OP_I386, I386OP(group0FBA_16), I386OP(group0FBA_32), true },
+ { 0xBB, OP_2BYTE|OP_I386, I386OP(btc_rm16_r16), I386OP(btc_rm32_r32), true },
+ { 0xBC, OP_2BYTE|OP_I386, I386OP(bsf_r16_rm16), I386OP(bsf_r32_rm32), false},
+ { 0xBD, OP_2BYTE|OP_I386, I386OP(bsr_r16_rm16), I386OP(bsr_r32_rm32), false},
+ { 0xBE, OP_2BYTE|OP_I386, I386OP(movsx_r16_rm8), I386OP(movsx_r32_rm8), false},
+ { 0xBF, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movsx_r32_rm16), false},
+ { 0xC0, OP_2BYTE|OP_I486, I486OP(xadd_rm8_r8), I486OP(xadd_rm8_r8), true },
+ { 0xC1, OP_2BYTE|OP_I486, I486OP(xadd_rm16_r16), I486OP(xadd_rm32_r32), true },
+ { 0xC2, OP_2BYTE|OP_SSE, SSEOP(cmpps_r128_rm128_i8), SSEOP(cmpps_r128_rm128_i8), false},
+ { 0xC3, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movnti_m16_r16), PENTIUMOP(movnti_m32_r32), false},
+ { 0xC4, OP_2BYTE|OP_SSE, SSEOP(pinsrw_r64_r16m16_i8), SSEOP(pinsrw_r64_r32m16_i8),false},
+ { 0xC5, OP_2BYTE|OP_SSE, SSEOP(pextrw_r16_r64_i8), SSEOP(pextrw_r32_r64_i8), false},
+ { 0xC6, OP_2BYTE|OP_SSE, SSEOP(shufps), SSEOP(shufps), false},
+ { 0xC7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmpxchg8b_m64), PENTIUMOP(cmpxchg8b_m64), true },
+ { 0xC8, OP_2BYTE|OP_I486, I486OP(bswap_eax), I486OP(bswap_eax), false},
+ { 0xC9, OP_2BYTE|OP_I486, I486OP(bswap_ecx), I486OP(bswap_ecx), false},
+ { 0xCA, OP_2BYTE|OP_I486, I486OP(bswap_edx), I486OP(bswap_edx), false},
+ { 0xCB, OP_2BYTE|OP_I486, I486OP(bswap_ebx), I486OP(bswap_ebx), false},
+ { 0xCC, OP_2BYTE|OP_I486, I486OP(bswap_esp), I486OP(bswap_esp), false},
+ { 0xCD, OP_2BYTE|OP_I486, I486OP(bswap_ebp), I486OP(bswap_ebp), false},
+ { 0xCE, OP_2BYTE|OP_I486, I486OP(bswap_esi), I486OP(bswap_esi), false},
+ { 0xCF, OP_2BYTE|OP_I486, I486OP(bswap_edi), I486OP(bswap_edi), false},
+ { 0xD1, OP_2BYTE|OP_MMX, MMXOP(psrlw_r64_rm64), MMXOP(psrlw_r64_rm64), false},
+ { 0xD2, OP_2BYTE|OP_MMX, MMXOP(psrld_r64_rm64), MMXOP(psrld_r64_rm64), false},
+ { 0xD3, OP_2BYTE|OP_MMX, MMXOP(psrlq_r64_rm64), MMXOP(psrlq_r64_rm64), false},
+ { 0xD4, OP_2BYTE|OP_MMX, MMXOP(paddq_r64_rm64), MMXOP(paddq_r64_rm64), false},
+ { 0xD5, OP_2BYTE|OP_MMX, MMXOP(pmullw_r64_rm64), MMXOP(pmullw_r64_rm64), false},
+ { 0xD7, OP_2BYTE|OP_SSE, SSEOP(pmovmskb_r16_r64), SSEOP(pmovmskb_r32_r64), false},
+ { 0xD8, OP_2BYTE|OP_MMX, MMXOP(psubusb_r64_rm64), MMXOP(psubusb_r64_rm64), false},
+ { 0xD9, OP_2BYTE|OP_MMX, MMXOP(psubusw_r64_rm64), MMXOP(psubusw_r64_rm64), false},
+ { 0xDA, OP_2BYTE|OP_SSE, SSEOP(pminub_r64_rm64), SSEOP(pminub_r64_rm64), false},
+ { 0xDB, OP_2BYTE|OP_MMX, MMXOP(pand_r64_rm64), MMXOP(pand_r64_rm64), false},
+ { 0xDC, OP_2BYTE|OP_MMX, MMXOP(paddusb_r64_rm64), MMXOP(paddusb_r64_rm64), false},
+ { 0xDD, OP_2BYTE|OP_MMX, MMXOP(paddusw_r64_rm64), MMXOP(paddusw_r64_rm64), false},
+ { 0xDE, OP_2BYTE|OP_SSE, SSEOP(pmaxub_r64_rm64), SSEOP(pmaxub_r64_rm64), false},
+ { 0xDF, OP_2BYTE|OP_MMX, MMXOP(pandn_r64_rm64), MMXOP(pandn_r64_rm64), false},
+ { 0xE0, OP_2BYTE|OP_SSE, SSEOP(pavgb_r64_rm64), SSEOP(pavgb_r64_rm64), false},
+ { 0xE1, OP_2BYTE|OP_MMX, MMXOP(psraw_r64_rm64), MMXOP(psraw_r64_rm64), false},
+ { 0xE2, OP_2BYTE|OP_MMX, MMXOP(psrad_r64_rm64), MMXOP(psrad_r64_rm64), false},
+ { 0xE3, OP_2BYTE|OP_SSE, SSEOP(pavgw_r64_rm64), SSEOP(pavgw_r64_rm64), false},
+ { 0xE4, OP_2BYTE|OP_SSE, SSEOP(pmulhuw_r64_rm64), SSEOP(pmulhuw_r64_rm64), false},
+ { 0xE5, OP_2BYTE|OP_MMX, MMXOP(pmulhw_r64_rm64), MMXOP(pmulhw_r64_rm64), false},
+ { 0xE7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movntq_m64_r64), PENTIUMOP(movntq_m64_r64), false},
+ { 0xE8, OP_2BYTE|OP_MMX, MMXOP(psubsb_r64_rm64), MMXOP(psubsb_r64_rm64), false},
+ { 0xE9, OP_2BYTE|OP_MMX, MMXOP(psubsw_r64_rm64), MMXOP(psubsw_r64_rm64), false},
+ { 0xEA, OP_2BYTE|OP_SSE, SSEOP(pminsw_r64_rm64), SSEOP(pminsw_r64_rm64), false},
+ { 0xEB, OP_2BYTE|OP_MMX, MMXOP(por_r64_rm64), MMXOP(por_r64_rm64), false},
+ { 0xEC, OP_2BYTE|OP_MMX, MMXOP(paddsb_r64_rm64), MMXOP(paddsb_r64_rm64), false},
+ { 0xED, OP_2BYTE|OP_MMX, MMXOP(paddsw_r64_rm64), MMXOP(paddsw_r64_rm64), false},
+ { 0xEE, OP_2BYTE|OP_SSE, SSEOP(pmaxsw_r64_rm64), SSEOP(pmaxsw_r64_rm64), false},
+ { 0xEF, OP_2BYTE|OP_MMX, MMXOP(pxor_r64_rm64), MMXOP(pxor_r64_rm64), false},
+ { 0xF1, OP_2BYTE|OP_MMX, MMXOP(psllw_r64_rm64), MMXOP(psllw_r64_rm64), false},
+ { 0xF2, OP_2BYTE|OP_MMX, MMXOP(pslld_r64_rm64), MMXOP(pslld_r64_rm64), false},
+ { 0xF3, OP_2BYTE|OP_MMX, MMXOP(psllq_r64_rm64), MMXOP(psllq_r64_rm64), false},
+ { 0xF4, OP_2BYTE|OP_SSE, SSEOP(pmuludq_r64_rm64), SSEOP(pmuludq_r64_rm64), false},
+ { 0xF5, OP_2BYTE|OP_MMX, MMXOP(pmaddwd_r64_rm64), MMXOP(pmaddwd_r64_rm64), false},
+ { 0xF6, OP_2BYTE|OP_SSE, SSEOP(psadbw_r64_rm64), SSEOP(psadbw_r64_rm64), false},
+ { 0xf7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(maskmovq_r64_r64), PENTIUMOP(maskmovq_r64_r64),false},
+ { 0xF8, OP_2BYTE|OP_MMX, MMXOP(psubb_r64_rm64), MMXOP(psubb_r64_rm64), false},
+ { 0xF9, OP_2BYTE|OP_MMX, MMXOP(psubw_r64_rm64), MMXOP(psubw_r64_rm64), false},
+ { 0xFA, OP_2BYTE|OP_MMX, MMXOP(psubd_r64_rm64), MMXOP(psubd_r64_rm64), false},
+ { 0xFB, OP_2BYTE|OP_SSE, SSEOP(psubq_r64_rm64), SSEOP(psubq_r64_rm64), false},
+ { 0xFC, OP_2BYTE|OP_MMX, MMXOP(paddb_r64_rm64), MMXOP(paddb_r64_rm64), false},
+ { 0xFD, OP_2BYTE|OP_MMX, MMXOP(paddw_r64_rm64), MMXOP(paddw_r64_rm64), false},
+ { 0xFE, OP_2BYTE|OP_MMX, MMXOP(paddd_r64_rm64), MMXOP(paddd_r64_rm64), false},
+ /* F3 0F ?? */
+ { 0x10, OP_3BYTEF3|OP_SSE, SSEOP(movss_r128_rm128), SSEOP(movss_r128_rm128), false},
+ { 0x11, OP_3BYTEF3|OP_SSE, SSEOP(movss_rm128_r128), SSEOP(movss_rm128_r128), false},
+ { 0x12, OP_3BYTEF3|OP_SSE, SSEOP(movsldup_r128_rm128), SSEOP(movsldup_r128_rm128), false},
+ { 0x16, OP_3BYTEF3|OP_SSE, SSEOP(movshdup_r128_rm128), SSEOP(movshdup_r128_rm128), false},
+ { 0x2A, OP_3BYTEF3|OP_SSE, SSEOP(cvtsi2ss_r128_rm32), SSEOP(cvtsi2ss_r128_rm32), false},
+ { 0x2C, OP_3BYTEF3|OP_SSE, SSEOP(cvttss2si_r32_r128m32), SSEOP(cvttss2si_r32_r128m32),false},
+ { 0x2D, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2si_r32_r128m32), SSEOP(cvtss2si_r32_r128m32),false},
+ { 0x51, OP_3BYTEF3|OP_SSE, SSEOP(sqrtss_r128_r128m32), SSEOP(sqrtss_r128_r128m32), false},
+ { 0x52, OP_3BYTEF3|OP_SSE, SSEOP(rsqrtss_r128_r128m32), SSEOP(rsqrtss_r128_r128m32),false},
+ { 0x53, OP_3BYTEF3|OP_SSE, SSEOP(rcpss_r128_r128m32), SSEOP(rcpss_r128_r128m32), false},
+ { 0x58, OP_3BYTEF3|OP_SSE, SSEOP(addss), SSEOP(addss), false},
+ { 0x59, OP_3BYTEF3|OP_SSE, SSEOP(mulss), SSEOP(mulss), false},
+ { 0x5A, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2sd_r128_r128m32), SSEOP(cvtss2sd_r128_r128m32),false},
+ { 0x5B, OP_3BYTEF3|OP_SSE, SSEOP(cvttps2dq_r128_rm128), SSEOP(cvttps2dq_r128_rm128),false},
+ { 0x5C, OP_3BYTEF3|OP_SSE, SSEOP(subss), SSEOP(subss), false},
+ { 0x5D, OP_3BYTEF3|OP_SSE, SSEOP(minss_r128_r128m32), SSEOP(minss_r128_r128m32), false},
+ { 0x5E, OP_3BYTEF3|OP_SSE, SSEOP(divss), SSEOP(divss), false},
+ { 0x5F, OP_3BYTEF3|OP_SSE, SSEOP(maxss_r128_r128m32), SSEOP(maxss_r128_r128m32), false},
+ { 0x6F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_r128_rm128), SSEOP(movdqu_r128_rm128), false},
+ { 0x70, OP_3BYTEF3|OP_SSE, SSEOP(pshufhw_r128_rm128_i8), SSEOP(pshufhw_r128_rm128_i8),false},
+ { 0x7E, OP_3BYTEF3|OP_SSE, SSEOP(movq_r128_r128m64), SSEOP(movq_r128_r128m64), false},
+ { 0x7F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_rm128_r128), SSEOP(movdqu_rm128_r128), false},
+ { 0xAE, OP_3BYTE66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xB8, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(popcnt_r16_rm16), PENTIUMOP(popcnt_r32_rm32), false},
+ { 0xBC, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(tzcnt_r16_rm16), PENTIUMOP(tzcnt_r32_rm32), false},
+ { 0xC2, OP_3BYTEF3|OP_SSE, SSEOP(cmpss_r128_r128m32_i8), SSEOP(cmpss_r128_r128m32_i8),false},
+ { 0xC7, OP_3BYTEF2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xD6, OP_3BYTEF3|OP_SSE, SSEOP(movq2dq_r128_r64), SSEOP(movq2dq_r128_r64), false},
+ { 0xE6, OP_3BYTEF3|OP_SSE, SSEOP(cvtdq2pd_r128_r128m64), SSEOP(cvtdq2pd_r128_r128m64),false},
+ /* F2 0F ?? */
+ { 0x10, OP_3BYTEF2|OP_SSE, SSEOP(movsd_r128_r128m64), SSEOP(movsd_r128_r128m64), false},
+ { 0x11, OP_3BYTEF2|OP_SSE, SSEOP(movsd_r128m64_r128), SSEOP(movsd_r128m64_r128), false},
+ { 0x12, OP_3BYTEF2|OP_SSE, SSEOP(movddup_r128_r128m64), SSEOP(movddup_r128_r128m64),false},
+ { 0x2A, OP_3BYTEF2|OP_SSE, SSEOP(cvtsi2sd_r128_rm32), SSEOP(cvtsi2sd_r128_rm32), false},
+ { 0x2C, OP_3BYTEF2|OP_SSE, SSEOP(cvttsd2si_r32_r128m64), SSEOP(cvttsd2si_r32_r128m64),false},
+ { 0x2D, OP_3BYTEF2|OP_SSE, SSEOP(cvtsd2si_r32_r128m64), SSEOP(cvtsd2si_r32_r128m64),false},
+ { 0x51, OP_3BYTEF2|OP_SSE, SSEOP(sqrtsd_r128_r128m64), SSEOP(sqrtsd_r128_r128m64), false},
+ { 0x58, OP_3BYTEF2|OP_SSE, SSEOP(addsd_r128_r128m64), SSEOP(addsd_r128_r128m64), false},
+ { 0x59, OP_3BYTEF2|OP_SSE, SSEOP(mulsd_r128_r128m64), SSEOP(mulsd_r128_r128m64), false},
+ { 0x5A, OP_3BYTEF2|OP_SSE, SSEOP(cvtsd2ss_r128_r128m64), SSEOP(cvtsd2ss_r128_r128m64),false},
+ { 0x5C, OP_3BYTEF2|OP_SSE, SSEOP(subsd_r128_r128m64), SSEOP(subsd_r128_r128m64), false},
+ { 0x5D, OP_3BYTEF2|OP_SSE, SSEOP(minsd_r128_r128m64), SSEOP(minsd_r128_r128m64), false},
+ { 0x5E, OP_3BYTEF2|OP_SSE, SSEOP(divsd_r128_r128m64), SSEOP(divsd_r128_r128m64), false},
+ { 0x5F, OP_3BYTEF2|OP_SSE, SSEOP(maxsd_r128_r128m64), SSEOP(maxsd_r128_r128m64), false},
+ { 0x70, OP_3BYTEF2|OP_SSE, SSEOP(pshuflw_r128_rm128_i8), SSEOP(pshuflw_r128_rm128_i8),false},
+ { 0x7C, OP_3BYTEF2|OP_SSE, SSEOP(haddps_r128_rm128), SSEOP(haddps_r128_rm128), false},
+ { 0x7D, OP_3BYTEF2|OP_SSE, SSEOP(hsubps_r128_rm128), SSEOP(hsubps_r128_rm128), false},
+ { 0xC2, OP_3BYTEF2|OP_SSE, SSEOP(cmpsd_r128_r128m64_i8), SSEOP(cmpsd_r128_r128m64_i8),false},
+ { 0xD0, OP_3BYTEF2|OP_SSE, SSEOP(addsubps_r128_rm128), SSEOP(addsubps_r128_rm128), false},
+ { 0xD6, OP_3BYTEF2|OP_SSE, SSEOP(movdq2q_r64_r128), SSEOP(movdq2q_r64_r128), false},
+ { 0xE6, OP_3BYTEF2|OP_SSE, SSEOP(cvtpd2dq_r128_rm128), SSEOP(cvtpd2dq_r128_rm128), false},
+ { 0xF0, OP_3BYTEF2|OP_SSE, SSEOP(lddqu_r128_m128), SSEOP(lddqu_r128_m128), false},
+ /* 66 0F ?? */
+ { 0x10, OP_3BYTE66|OP_SSE, SSEOP(movupd_r128_rm128), SSEOP(movupd_r128_rm128), false},
+ { 0x11, OP_3BYTE66|OP_SSE, SSEOP(movupd_rm128_r128), SSEOP(movupd_rm128_r128), false},
+ { 0x12, OP_3BYTE66|OP_SSE, SSEOP(movlpd_r128_m64), SSEOP(movlpd_r128_m64), false},
+ { 0x13, OP_3BYTE66|OP_SSE, SSEOP(movlpd_m64_r128), SSEOP(movlpd_m64_r128), false},
+ { 0x14, OP_3BYTE66|OP_SSE, SSEOP(unpcklpd_r128_rm128), SSEOP(unpcklpd_r128_rm128), false},
+ { 0x15, OP_3BYTE66|OP_SSE, SSEOP(unpckhpd_r128_rm128), SSEOP(unpckhpd_r128_rm128), false},
+ { 0x16, OP_3BYTE66|OP_SSE, SSEOP(movhpd_r128_m64), SSEOP(movhpd_r128_m64), false},
+ { 0x17, OP_3BYTE66|OP_SSE, SSEOP(movhpd_m64_r128), SSEOP(movhpd_m64_r128), false},
+ { 0x28, OP_3BYTE66|OP_SSE, SSEOP(movapd_r128_rm128), SSEOP(movapd_r128_rm128), false},
+ { 0x29, OP_3BYTE66|OP_SSE, SSEOP(movapd_rm128_r128), SSEOP(movapd_rm128_r128), false},
+ { 0x2A, OP_3BYTE66|OP_SSE, SSEOP(cvtpi2pd_r128_rm64), SSEOP(cvtpi2pd_r128_rm64), false},
+ { 0x2B, OP_3BYTE66|OP_SSE, SSEOP(movntpd_m128_r128), SSEOP(movntpd_m128_r128), false},
+ { 0x2C, OP_3BYTE66|OP_SSE, SSEOP(cvttpd2pi_r64_rm128), SSEOP(cvttpd2pi_r64_rm128), false},
+ { 0x2D, OP_3BYTE66|OP_SSE, SSEOP(cvtpd2pi_r64_rm128), SSEOP(cvtpd2pi_r64_rm128), false},
+ { 0x2E, OP_3BYTE66|OP_SSE, SSEOP(ucomisd_r128_r128m64), SSEOP(ucomisd_r128_r128m64),false},
+ { 0x2F, OP_3BYTE66|OP_SSE, SSEOP(comisd_r128_r128m64), SSEOP(comisd_r128_r128m64), false},
+ { 0x50, OP_3BYTE66|OP_SSE, SSEOP(movmskpd_r32_r128), SSEOP(movmskpd_r32_r128), false},
+ { 0x51, OP_3BYTE66|OP_SSE, SSEOP(sqrtpd_r128_rm128), SSEOP(sqrtpd_r128_rm128), false},
+ { 0x54, OP_3BYTE66|OP_SSE, SSEOP(andpd_r128_rm128), SSEOP(andpd_r128_rm128), false},
+ { 0x55, OP_3BYTE66|OP_SSE, SSEOP(andnpd_r128_rm128), SSEOP(andnpd_r128_rm128), false},
+ { 0x56, OP_3BYTE66|OP_SSE, SSEOP(orpd_r128_rm128), SSEOP(orpd_r128_rm128), false},
+ { 0x57, OP_3BYTE66|OP_SSE, SSEOP(xorpd_r128_rm128), SSEOP(xorpd_r128_rm128), false},
+ { 0x58, OP_3BYTE66|OP_SSE, SSEOP(addpd_r128_rm128), SSEOP(addpd_r128_rm128), false},
+ { 0x59, OP_3BYTE66|OP_SSE, SSEOP(mulpd_r128_rm128), SSEOP(mulpd_r128_rm128), false},
+ { 0x5A, OP_3BYTE66|OP_SSE, SSEOP(cvtpd2ps_r128_rm128), SSEOP(cvtpd2ps_r128_rm128), false},
+ { 0x5B, OP_3BYTE66|OP_SSE, SSEOP(cvtps2dq_r128_rm128), SSEOP(cvtps2dq_r128_rm128), false},
+ { 0x5C, OP_3BYTE66|OP_SSE, SSEOP(subpd_r128_rm128), SSEOP(subpd_r128_rm128), false},
+ { 0x5D, OP_3BYTE66|OP_SSE, SSEOP(minpd_r128_rm128), SSEOP(minpd_r128_rm128), false},
+ { 0x5E, OP_3BYTE66|OP_SSE, SSEOP(divpd_r128_rm128), SSEOP(divpd_r128_rm128), false},
+ { 0x5F, OP_3BYTE66|OP_SSE, SSEOP(maxpd_r128_rm128), SSEOP(maxpd_r128_rm128), false},
+ { 0x60, OP_3BYTE66|OP_SSE, SSEOP(punpcklbw_r128_rm128), SSEOP(punpcklbw_r128_rm128),false},
+ { 0x61, OP_3BYTE66|OP_SSE, SSEOP(punpcklwd_r128_rm128), SSEOP(punpcklwd_r128_rm128),false},
+ { 0x62, OP_3BYTE66|OP_SSE, SSEOP(punpckldq_r128_rm128), SSEOP(punpckldq_r128_rm128),false},
+ { 0x63, OP_3BYTE66|OP_SSE, SSEOP(packsswb_r128_rm128), SSEOP(packsswb_r128_rm128), false},
+ { 0x64, OP_3BYTE66|OP_SSE, SSEOP(pcmpgtb_r128_rm128), SSEOP(pcmpgtb_r128_rm128), false},
+ { 0x65, OP_3BYTE66|OP_SSE, SSEOP(pcmpgtw_r128_rm128), SSEOP(pcmpgtw_r128_rm128), false},
+ { 0x66, OP_3BYTE66|OP_SSE, SSEOP(pcmpgtd_r128_rm128), SSEOP(pcmpgtd_r128_rm128), false},
+ { 0x67, OP_3BYTE66|OP_SSE, SSEOP(packuswb_r128_rm128), SSEOP(packuswb_r128_rm128), false},
+ { 0x68, OP_3BYTE66|OP_SSE, SSEOP(punpckhbw_r128_rm128), SSEOP(punpckhbw_r128_rm128),false},
+ { 0x69, OP_3BYTE66|OP_SSE, SSEOP(punpckhwd_r128_rm128), SSEOP(punpckhwd_r128_rm128),false},
+ { 0x6A, OP_3BYTE66|OP_SSE, SSEOP(unpckhdq_r128_rm128), SSEOP(unpckhdq_r128_rm128), false},
+ { 0x6B, OP_3BYTE66|OP_SSE, SSEOP(packssdw_r128_rm128), SSEOP(packssdw_r128_rm128), false},
+ { 0x6C, OP_3BYTE66|OP_SSE, SSEOP(punpcklqdq_r128_rm128), SSEOP(punpcklqdq_r128_rm128),false},
+ { 0x6D, OP_3BYTE66|OP_SSE, SSEOP(punpckhqdq_r128_rm128), SSEOP(punpckhqdq_r128_rm128),false},
+ { 0x6E, OP_3BYTE66|OP_SSE, SSEOP(movd_m128_rm32), SSEOP(movd_m128_rm32), false},
+ { 0x6F, OP_3BYTE66|OP_SSE, SSEOP(movdqa_m128_rm128), SSEOP(movdqa_m128_rm128), false},
+ { 0x70, OP_3BYTE66|OP_SSE, SSEOP(pshufd_r128_rm128_i8), SSEOP(pshufd_r128_rm128_i8),false},
+ { 0x71, OP_3BYTE66|OP_SSE, SSEOP(group_660f71), SSEOP(group_660f71), false},
+ { 0x72, OP_3BYTE66|OP_SSE, SSEOP(group_660f72), SSEOP(group_660f72), false},
+ { 0x73, OP_3BYTE66|OP_SSE, SSEOP(group_660f73), SSEOP(group_660f73), false},
+ { 0x74, OP_3BYTE66|OP_SSE, SSEOP(pcmpeqb_r128_rm128), SSEOP(pcmpeqb_r128_rm128), false},
+ { 0x75, OP_3BYTE66|OP_SSE, SSEOP(pcmpeqw_r128_rm128), SSEOP(pcmpeqw_r128_rm128), false},
+ { 0x76, OP_3BYTE66|OP_SSE, SSEOP(pcmpeqd_r128_rm128), SSEOP(pcmpeqd_r128_rm128), false},
+ { 0x7C, OP_3BYTE66|OP_SSE, SSEOP(haddpd_r128_rm128), SSEOP(haddpd_r128_rm128), false},
+ { 0x7D, OP_3BYTE66|OP_SSE, SSEOP(hsubpd_r128_rm128), SSEOP(hsubpd_r128_rm128), false},
+ { 0x7E, OP_3BYTE66|OP_SSE, SSEOP(movd_rm32_r128), SSEOP(movd_rm32_r128), false},
+ { 0x7F, OP_3BYTE66|OP_SSE, SSEOP(movdqa_rm128_r128), SSEOP(movdqa_rm128_r128), false},
+ { 0xC2, OP_3BYTE66|OP_SSE, SSEOP(cmppd_r128_rm128_i8), SSEOP(cmppd_r128_rm128_i8), false},
+ { 0xC4, OP_3BYTE66|OP_SSE, SSEOP(pinsrw_r128_r32m16_i8), SSEOP(pinsrw_r128_r32m16_i8),false},
+ { 0xC5, OP_3BYTE66|OP_SSE, SSEOP(pextrw_reg_r128_i8), SSEOP(pextrw_reg_r128_i8), false},
+ { 0xC6, OP_3BYTE66|OP_SSE, SSEOP(shufpd_r128_rm128_i8), SSEOP(shufpd_r128_rm128_i8),false},
+ { 0xC7, OP_3BYTE66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xD0, OP_3BYTE66|OP_SSE, SSEOP(addsubpd_r128_rm128), SSEOP(addsubpd_r128_rm128), false},
+ { 0xD1, OP_3BYTE66|OP_SSE, SSEOP(psrlw_r128_rm128), SSEOP(psrlw_r128_rm128), false},
+ { 0xD2, OP_3BYTE66|OP_SSE, SSEOP(psrld_r128_rm128), SSEOP(psrld_r128_rm128), false},
+ { 0xD3, OP_3BYTE66|OP_SSE, SSEOP(psrlq_r128_rm128), SSEOP(psrlq_r128_rm128), false},
+ { 0xD4, OP_3BYTE66|OP_SSE, SSEOP(paddq_r128_rm128), SSEOP(paddq_r128_rm128), false},
+ { 0xD5, OP_3BYTE66|OP_SSE, SSEOP(pmullw_r128_rm128), SSEOP(pmullw_r128_rm128), false},
+ { 0xD6, OP_3BYTE66|OP_SSE, SSEOP(movq_r128m64_r128), SSEOP(movq_r128m64_r128), false},
+ { 0xD7, OP_3BYTE66|OP_SSE, SSEOP(pmovmskb_r32_r128), SSEOP(pmovmskb_r32_r128), false},
+ { 0xD8, OP_3BYTE66|OP_SSE, SSEOP(psubusb_r128_rm128), SSEOP(psubusb_r128_rm128), false},
+ { 0xD9, OP_3BYTE66|OP_SSE, SSEOP(psubusw_r128_rm128), SSEOP(psubusw_r128_rm128), false},
+ { 0xDA, OP_3BYTE66|OP_SSE, SSEOP(pminub_r128_rm128), SSEOP(pminub_r128_rm128), false},
+ { 0xDB, OP_3BYTE66|OP_SSE, SSEOP(pand_r128_rm128), SSEOP(pand_r128_rm128), false},
+ { 0xDC, OP_3BYTE66|OP_SSE, SSEOP(paddusb_r128_rm128), SSEOP(paddusb_r128_rm128), false},
+ { 0xDD, OP_3BYTE66|OP_SSE, SSEOP(paddusw_r128_rm128), SSEOP(paddusw_r128_rm128), false},
+ { 0xDE, OP_3BYTE66|OP_SSE, SSEOP(pmaxub_r128_rm128), SSEOP(pmaxub_r128_rm128), false},
+ { 0xDF, OP_3BYTE66|OP_SSE, SSEOP(pandn_r128_rm128), SSEOP(pandn_r128_rm128), false},
+ { 0xE0, OP_3BYTE66|OP_SSE, SSEOP(pavgb_r128_rm128), SSEOP(pavgb_r128_rm128), false},
+ { 0xE1, OP_3BYTE66|OP_SSE, SSEOP(psraw_r128_rm128), SSEOP(psraw_r128_rm128), false},
+ { 0xE2, OP_3BYTE66|OP_SSE, SSEOP(psrad_r128_rm128), SSEOP(psrad_r128_rm128), false},
+ { 0xE3, OP_3BYTE66|OP_SSE, SSEOP(pavgw_r128_rm128), SSEOP(pavgw_r128_rm128), false},
+ { 0xE4, OP_3BYTE66|OP_SSE, SSEOP(pmulhuw_r128_rm128), SSEOP(pmulhuw_r128_rm128), false},
+ { 0xE5, OP_3BYTE66|OP_SSE, SSEOP(pmulhw_r128_rm128), SSEOP(pmulhw_r128_rm128), false},
+ { 0xE6, OP_3BYTE66|OP_SSE, SSEOP(cvttpd2dq_r128_rm128), SSEOP(cvttpd2dq_r128_rm128),false},
+ { 0xE7, OP_3BYTE66|OP_SSE, SSEOP(movntdq_m128_r128), SSEOP(movntdq_m128_r128), false},
+ { 0xE8, OP_3BYTE66|OP_SSE, SSEOP(psubsb_r128_rm128), SSEOP(psubsb_r128_rm128), false},
+ { 0xE9, OP_3BYTE66|OP_SSE, SSEOP(psubsw_r128_rm128), SSEOP(psubsw_r128_rm128), false},
+ { 0xEA, OP_3BYTE66|OP_SSE, SSEOP(pminsw_r128_rm128), SSEOP(pminsw_r128_rm128), false},
+ { 0xEB, OP_3BYTE66|OP_SSE, SSEOP(por_r128_rm128), SSEOP(por_r128_rm128), false},
+ { 0xEC, OP_3BYTE66|OP_SSE, SSEOP(paddsb_r128_rm128), SSEOP(paddsb_r128_rm128), false},
+ { 0xED, OP_3BYTE66|OP_SSE, SSEOP(paddsw_r128_rm128), SSEOP(paddsw_r128_rm128), false},
+ { 0xEE, OP_3BYTE66|OP_SSE, SSEOP(pmaxsw_r128_rm128), SSEOP(pmaxsw_r128_rm128), false},
+ { 0xEF, OP_3BYTE66|OP_SSE, SSEOP(pxor_r128_rm128), SSEOP(pxor_r128_rm128), false},
+ { 0xF1, OP_3BYTE66|OP_SSE, SSEOP(psllw_r128_rm128), SSEOP(psllw_r128_rm128), false},
+ { 0xF2, OP_3BYTE66|OP_SSE, SSEOP(pslld_r128_rm128), SSEOP(pslld_r128_rm128), false},
+ { 0xF3, OP_3BYTE66|OP_SSE, SSEOP(psllq_r128_rm128), SSEOP(psllq_r128_rm128), false},
+ { 0xF4, OP_3BYTE66|OP_SSE, SSEOP(pmuludq_r128_rm128), SSEOP(pmuludq_r128_rm128), false},
+ { 0xF5, OP_3BYTE66|OP_SSE, SSEOP(pmaddwd_r128_rm128), SSEOP(pmaddwd_r128_rm128), false},
+ { 0xF6, OP_3BYTE66|OP_SSE, SSEOP(psadbw_r128_rm128), SSEOP(psadbw_r128_rm128), false},
+ { 0xF7, OP_3BYTE66|OP_SSE, SSEOP(maskmovdqu_r128_r128), SSEOP(maskmovdqu_r128_r128),false},
+ { 0xF8, OP_3BYTE66|OP_SSE, SSEOP(psubb_r128_rm128), SSEOP(psubb_r128_rm128), false},
+ { 0xF9, OP_3BYTE66|OP_SSE, SSEOP(psubw_r128_rm128), SSEOP(psubw_r128_rm128), false},
+ { 0xFA, OP_3BYTE66|OP_SSE, SSEOP(psubd_r128_rm128), SSEOP(psubd_r128_rm128), false},
+ { 0xFB, OP_3BYTE66|OP_SSE, SSEOP(psubq_r128_rm128), SSEOP(psubq_r128_rm128), false},
+ { 0xFC, OP_3BYTE66|OP_SSE, SSEOP(paddb_r128_rm128), SSEOP(paddb_r128_rm128), false},
+ { 0xFD, OP_3BYTE66|OP_SSE, SSEOP(paddw_r128_rm128), SSEOP(paddw_r128_rm128), false},
+ { 0xFE, OP_3BYTE66|OP_SSE, SSEOP(paddd_r128_rm128), SSEOP(paddd_r128_rm128), false},
+ /* 0F 38 ?? */
+ { 0x00, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x01, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x02, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x03, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x04, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x05, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x06, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x07, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x08, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x09, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0A, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0B, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1C, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1D, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1E, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF0, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF1, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF2, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF3, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF5, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF7, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ /* 0F 3A ?? */
+ { 0x0F, OP_3BYTE3A|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ /* 66 0F 38 ?? */
+ { 0x00, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x01, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x02, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x03, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x04, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x05, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x06, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x07, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x08, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x09, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x10, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x13, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x14, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x15, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x16, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x17, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x18, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x19, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x20, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x21, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x22, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x23, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x24, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x25, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x28, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x29, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x2A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x2B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x2C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x2D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x2E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x2F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x30, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x31, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x32, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x33, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x34, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x35, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x36, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x37, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x38, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x39, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x3A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x3B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x3C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x3D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x3E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x3F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x40, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x41, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x45, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x46, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x47, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x58, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x59, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x5A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x78, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x79, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x80, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x81, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x82, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x8C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x8E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x90, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x91, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x92, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x93, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x96, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x97, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x98, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x99, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x9A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x9B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x9C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x9D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x9E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x9F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xA6, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xA7, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xA8, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xA9, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xAA, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xAB, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xAC, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xAD, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xAE, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xAF, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xB6, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xB7, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xB8, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xB9, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xBA, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xBB, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xBC, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xBD, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xBE, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xBF, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xDB, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xDC, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xDD, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xDE, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xDF, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF0, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF1, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF3, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF6, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF7, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ /* F2 0F 38 ?? */
+ { 0xF0, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF1, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF3, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF5, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF6, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF7, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ /* F3 0F 38 ?? */
+ { 0xF3, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF5, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF6, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xF7, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ /* 66 0F 3A ?? */
+ { 0x00, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x01, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x02, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x04, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x05, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x06, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x08, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x09, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0A, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0B, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0C, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0D, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0E, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x0F, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x14, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x15, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x16, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x17, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x18, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x19, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x1D, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x20, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x21, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x22, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x38, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x39, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x40, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x41, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x42, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x44, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x46, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x4A, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x4B, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x4C, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x60, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x61, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x62, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0x63, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ { 0xDF, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
+ /* F2 0F 3A ?? */
+ { 0xF0, OP_4BYTE3AF2|OP_SSE, I386OP(invalid), I386OP(invalid), false}
+};
+++ /dev/null
-
-const X86_OPCODE x86_opcode_table[] =
-{
-// Opcode Flags 16-bit handler 32-bit handler
- { 0x00, OP_I386, I386OP(add_rm8_r8), I386OP(add_rm8_r8), true },
- { 0x01, OP_I386, I386OP(add_rm16_r16), I386OP(add_rm32_r32), true },
- { 0x02, OP_I386, I386OP(add_r8_rm8), I386OP(add_r8_rm8), false},
- { 0x03, OP_I386, I386OP(add_r16_rm16), I386OP(add_r32_rm32), false},
- { 0x04, OP_I386, I386OP(add_al_i8), I386OP(add_al_i8), false},
- { 0x05, OP_I386, I386OP(add_ax_i16), I386OP(add_eax_i32), false},
- { 0x06, OP_I386, I386OP(push_es16), I386OP(push_es32), false},
- { 0x07, OP_I386, I386OP(pop_es16), I386OP(pop_es32), false},
- { 0x08, OP_I386, I386OP(or_rm8_r8), I386OP(or_rm8_r8), true },
- { 0x09, OP_I386, I386OP(or_rm16_r16), I386OP(or_rm32_r32), true },
- { 0x0A, OP_I386, I386OP(or_r8_rm8), I386OP(or_r8_rm8), false},
- { 0x0B, OP_I386, I386OP(or_r16_rm16), I386OP(or_r32_rm32), false},
- { 0x0C, OP_I386, I386OP(or_al_i8), I386OP(or_al_i8), false},
- { 0x0D, OP_I386, I386OP(or_ax_i16), I386OP(or_eax_i32), false},
- { 0x0E, OP_I386, I386OP(push_cs16), I386OP(push_cs32), false},
- { 0x0F, OP_I386, I386OP(decode_two_byte), I386OP(decode_two_byte), true },
- { 0x10, OP_I386, I386OP(adc_rm8_r8), I386OP(adc_rm8_r8), true },
- { 0x11, OP_I386, I386OP(adc_rm16_r16), I386OP(adc_rm32_r32), true },
- { 0x12, OP_I386, I386OP(adc_r8_rm8), I386OP(adc_r8_rm8), false},
- { 0x13, OP_I386, I386OP(adc_r16_rm16), I386OP(adc_r32_rm32), false},
- { 0x14, OP_I386, I386OP(adc_al_i8), I386OP(adc_al_i8), false},
- { 0x15, OP_I386, I386OP(adc_ax_i16), I386OP(adc_eax_i32), false},
- { 0x16, OP_I386, I386OP(push_ss16), I386OP(push_ss32), false},
- { 0x17, OP_I386, I386OP(pop_ss16), I386OP(pop_ss32), false},
- { 0x18, OP_I386, I386OP(sbb_rm8_r8), I386OP(sbb_rm8_r8), true },
- { 0x19, OP_I386, I386OP(sbb_rm16_r16), I386OP(sbb_rm32_r32), true },
- { 0x1A, OP_I386, I386OP(sbb_r8_rm8), I386OP(sbb_r8_rm8), false},
- { 0x1B, OP_I386, I386OP(sbb_r16_rm16), I386OP(sbb_r32_rm32), false},
- { 0x1C, OP_I386, I386OP(sbb_al_i8), I386OP(sbb_al_i8), false},
- { 0x1D, OP_I386, I386OP(sbb_ax_i16), I386OP(sbb_eax_i32), false},
- { 0x1E, OP_I386, I386OP(push_ds16), I386OP(push_ds32), false},
- { 0x1F, OP_I386, I386OP(pop_ds16), I386OP(pop_ds32), false},
- { 0x20, OP_I386, I386OP(and_rm8_r8), I386OP(and_rm8_r8), true },
- { 0x21, OP_I386, I386OP(and_rm16_r16), I386OP(and_rm32_r32), true },
- { 0x22, OP_I386, I386OP(and_r8_rm8), I386OP(and_r8_rm8), false},
- { 0x23, OP_I386, I386OP(and_r16_rm16), I386OP(and_r32_rm32), false},
- { 0x24, OP_I386, I386OP(and_al_i8), I386OP(and_al_i8), false},
- { 0x25, OP_I386, I386OP(and_ax_i16), I386OP(and_eax_i32), false},
- { 0x26, OP_I386, I386OP(segment_ES), I386OP(segment_ES), false},
- { 0x27, OP_I386, I386OP(daa), I386OP(daa), false},
- { 0x28, OP_I386, I386OP(sub_rm8_r8), I386OP(sub_rm8_r8), true },
- { 0x29, OP_I386, I386OP(sub_rm16_r16), I386OP(sub_rm32_r32), true },
- { 0x2A, OP_I386, I386OP(sub_r8_rm8), I386OP(sub_r8_rm8), false},
- { 0x2B, OP_I386, I386OP(sub_r16_rm16), I386OP(sub_r32_rm32), false},
- { 0x2C, OP_I386, I386OP(sub_al_i8), I386OP(sub_al_i8), false},
- { 0x2D, OP_I386, I386OP(sub_ax_i16), I386OP(sub_eax_i32), false},
- { 0x2E, OP_I386, I386OP(segment_CS), I386OP(segment_CS), false},
- { 0x2F, OP_I386, I386OP(das), I386OP(das), false},
- { 0x30, OP_I386, I386OP(xor_rm8_r8), I386OP(xor_rm8_r8), true },
- { 0x31, OP_I386, I386OP(xor_rm16_r16), I386OP(xor_rm32_r32), true },
- { 0x32, OP_I386, I386OP(xor_r8_rm8), I386OP(xor_r8_rm8), false},
- { 0x33, OP_I386, I386OP(xor_r16_rm16), I386OP(xor_r32_rm32), false},
- { 0x34, OP_I386, I386OP(xor_al_i8), I386OP(xor_al_i8), false},
- { 0x35, OP_I386, I386OP(xor_ax_i16), I386OP(xor_eax_i32), false},
- { 0x36, OP_I386, I386OP(segment_SS), I386OP(segment_SS), false},
- { 0x37, OP_I386, I386OP(aaa), I386OP(aaa), false},
- { 0x38, OP_I386, I386OP(cmp_rm8_r8), I386OP(cmp_rm8_r8), false},
- { 0x39, OP_I386, I386OP(cmp_rm16_r16), I386OP(cmp_rm32_r32), false},
- { 0x3A, OP_I386, I386OP(cmp_r8_rm8), I386OP(cmp_r8_rm8), false},
- { 0x3B, OP_I386, I386OP(cmp_r16_rm16), I386OP(cmp_r32_rm32), false},
- { 0x3C, OP_I386, I386OP(cmp_al_i8), I386OP(cmp_al_i8), false},
- { 0x3D, OP_I386, I386OP(cmp_ax_i16), I386OP(cmp_eax_i32), false},
- { 0x3E, OP_I386, I386OP(segment_DS), I386OP(segment_DS), false},
- { 0x3F, OP_I386, I386OP(aas), I386OP(aas), false},
- { 0x40, OP_I386, I386OP(inc_ax), I386OP(inc_eax), false},
- { 0x41, OP_I386, I386OP(inc_cx), I386OP(inc_ecx), false},
- { 0x42, OP_I386, I386OP(inc_dx), I386OP(inc_edx), false},
- { 0x43, OP_I386, I386OP(inc_bx), I386OP(inc_ebx), false},
- { 0x44, OP_I386, I386OP(inc_sp), I386OP(inc_esp), false},
- { 0x45, OP_I386, I386OP(inc_bp), I386OP(inc_ebp), false},
- { 0x46, OP_I386, I386OP(inc_si), I386OP(inc_esi), false},
- { 0x47, OP_I386, I386OP(inc_di), I386OP(inc_edi), false},
- { 0x48, OP_I386, I386OP(dec_ax), I386OP(dec_eax), false},
- { 0x49, OP_I386, I386OP(dec_cx), I386OP(dec_ecx), false},
- { 0x4A, OP_I386, I386OP(dec_dx), I386OP(dec_edx), false},
- { 0x4B, OP_I386, I386OP(dec_bx), I386OP(dec_ebx), false},
- { 0x4C, OP_I386, I386OP(dec_sp), I386OP(dec_esp), false},
- { 0x4D, OP_I386, I386OP(dec_bp), I386OP(dec_ebp), false},
- { 0x4E, OP_I386, I386OP(dec_si), I386OP(dec_esi), false},
- { 0x4F, OP_I386, I386OP(dec_di), I386OP(dec_edi), false},
- { 0x50, OP_I386, I386OP(push_ax), I386OP(push_eax), false},
- { 0x51, OP_I386, I386OP(push_cx), I386OP(push_ecx), false},
- { 0x52, OP_I386, I386OP(push_dx), I386OP(push_edx), false},
- { 0x53, OP_I386, I386OP(push_bx), I386OP(push_ebx), false},
- { 0x54, OP_I386, I386OP(push_sp), I386OP(push_esp), false},
- { 0x55, OP_I386, I386OP(push_bp), I386OP(push_ebp), false},
- { 0x56, OP_I386, I386OP(push_si), I386OP(push_esi), false},
- { 0x57, OP_I386, I386OP(push_di), I386OP(push_edi), false},
- { 0x58, OP_I386, I386OP(pop_ax), I386OP(pop_eax), false},
- { 0x59, OP_I386, I386OP(pop_cx), I386OP(pop_ecx), false},
- { 0x5A, OP_I386, I386OP(pop_dx), I386OP(pop_edx), false},
- { 0x5B, OP_I386, I386OP(pop_bx), I386OP(pop_ebx), false},
- { 0x5C, OP_I386, I386OP(pop_sp), I386OP(pop_esp), false},
- { 0x5D, OP_I386, I386OP(pop_bp), I386OP(pop_ebp), false},
- { 0x5E, OP_I386, I386OP(pop_si), I386OP(pop_esi), false},
- { 0x5F, OP_I386, I386OP(pop_di), I386OP(pop_edi), false},
- { 0x60, OP_I386, I386OP(pusha), I386OP(pushad), false},
- { 0x61, OP_I386, I386OP(popa), I386OP(popad), false},
- { 0x62, OP_I386, I386OP(bound_r16_m16_m16), I386OP(bound_r32_m32_m32), false},
- { 0x63, OP_I386, I386OP(arpl), I386OP(arpl), false},
- { 0x64, OP_I386, I386OP(segment_FS), I386OP(segment_FS), false},
- { 0x65, OP_I386, I386OP(segment_GS), I386OP(segment_GS), false},
- { 0x66, OP_I386, I386OP(operand_size), I386OP(operand_size), false},
- { 0x67, OP_I386, I386OP(address_size), I386OP(address_size), false},
- { 0x68, OP_I386, I386OP(push_i16), I386OP(push_i32), false},
- { 0x69, OP_I386, I386OP(imul_r16_rm16_i16), I386OP(imul_r32_rm32_i32), false},
- { 0x6A, OP_I386, I386OP(push_i8), I386OP(push_i8), false},
- { 0x6B, OP_I386, I386OP(imul_r16_rm16_i8), I386OP(imul_r32_rm32_i8), false},
- { 0x6C, OP_I386, I386OP(insb), I386OP(insb), false},
- { 0x6D, OP_I386, I386OP(insw), I386OP(insd), false},
- { 0x6E, OP_I386, I386OP(outsb), I386OP(outsb), false},
- { 0x6F, OP_I386, I386OP(outsw), I386OP(outsd), false},
- { 0x70, OP_I386, I386OP(jo_rel8), I386OP(jo_rel8), false},
- { 0x71, OP_I386, I386OP(jno_rel8), I386OP(jno_rel8), false},
- { 0x72, OP_I386, I386OP(jc_rel8), I386OP(jc_rel8), false},
- { 0x73, OP_I386, I386OP(jnc_rel8), I386OP(jnc_rel8), false},
- { 0x74, OP_I386, I386OP(jz_rel8), I386OP(jz_rel8), false},
- { 0x75, OP_I386, I386OP(jnz_rel8), I386OP(jnz_rel8), false},
- { 0x76, OP_I386, I386OP(jbe_rel8), I386OP(jbe_rel8), false},
- { 0x77, OP_I386, I386OP(ja_rel8), I386OP(ja_rel8), false},
- { 0x78, OP_I386, I386OP(js_rel8), I386OP(js_rel8), false},
- { 0x79, OP_I386, I386OP(jns_rel8), I386OP(jns_rel8), false},
- { 0x7A, OP_I386, I386OP(jp_rel8), I386OP(jp_rel8), false},
- { 0x7B, OP_I386, I386OP(jnp_rel8), I386OP(jnp_rel8), false},
- { 0x7C, OP_I386, I386OP(jl_rel8), I386OP(jl_rel8), false},
- { 0x7D, OP_I386, I386OP(jge_rel8), I386OP(jge_rel8), false},
- { 0x7E, OP_I386, I386OP(jle_rel8), I386OP(jle_rel8), false},
- { 0x7F, OP_I386, I386OP(jg_rel8), I386OP(jg_rel8), false},
- { 0x80, OP_I386, I386OP(group80_8), I386OP(group80_8), true },
- { 0x81, OP_I386, I386OP(group81_16), I386OP(group81_32), true },
- { 0x82, OP_I386, I386OP(group80_8), I386OP(group80_8), true },
- { 0x83, OP_I386, I386OP(group83_16), I386OP(group83_32), true },
- { 0x84, OP_I386, I386OP(test_rm8_r8), I386OP(test_rm8_r8), false},
- { 0x85, OP_I386, I386OP(test_rm16_r16), I386OP(test_rm32_r32), false},
- { 0x86, OP_I386, I386OP(xchg_r8_rm8), I386OP(xchg_r8_rm8), true },
- { 0x87, OP_I386, I386OP(xchg_r16_rm16), I386OP(xchg_r32_rm32), true },
- { 0x88, OP_I386, I386OP(mov_rm8_r8), I386OP(mov_rm8_r8), false},
- { 0x89, OP_I386, I386OP(mov_rm16_r16), I386OP(mov_rm32_r32), false},
- { 0x8A, OP_I386, I386OP(mov_r8_rm8), I386OP(mov_r8_rm8), false},
- { 0x8B, OP_I386, I386OP(mov_r16_rm16), I386OP(mov_r32_rm32), false},
- { 0x8C, OP_I386, I386OP(mov_rm16_sreg), I386OP(mov_rm16_sreg), false},
- { 0x8D, OP_I386, I386OP(lea16), I386OP(lea32), false},
- { 0x8E, OP_I386, I386OP(mov_sreg_rm16), I386OP(mov_sreg_rm16), false},
- { 0x8F, OP_I386, I386OP(pop_rm16), I386OP(pop_rm32), false},
- { 0x90, OP_I386, I386OP(nop), I386OP(nop), false},
- { 0x91, OP_I386, I386OP(xchg_ax_cx), I386OP(xchg_eax_ecx), false},
- { 0x92, OP_I386, I386OP(xchg_ax_dx), I386OP(xchg_eax_edx), false},
- { 0x93, OP_I386, I386OP(xchg_ax_bx), I386OP(xchg_eax_ebx), false},
- { 0x94, OP_I386, I386OP(xchg_ax_sp), I386OP(xchg_eax_esp), false},
- { 0x95, OP_I386, I386OP(xchg_ax_bp), I386OP(xchg_eax_ebp), false},
- { 0x96, OP_I386, I386OP(xchg_ax_si), I386OP(xchg_eax_esi), false},
- { 0x97, OP_I386, I386OP(xchg_ax_di), I386OP(xchg_eax_edi), false},
- { 0x98, OP_I386, I386OP(cbw), I386OP(cwde), false},
- { 0x99, OP_I386, I386OP(cwd), I386OP(cdq), false},
- { 0x9A, OP_I386, I386OP(call_abs16), I386OP(call_abs32), false},
- { 0x9B, OP_I386, I386OP(wait), I386OP(wait), false},
- { 0x9C, OP_I386, I386OP(pushf), I386OP(pushfd), false},
- { 0x9D, OP_I386, I386OP(popf), I386OP(popfd), false},
- { 0x9E, OP_I386, I386OP(sahf), I386OP(sahf), false},
- { 0x9F, OP_I386, I386OP(lahf), I386OP(lahf), false},
- { 0xA0, OP_I386, I386OP(mov_al_m8), I386OP(mov_al_m8), false},
- { 0xA1, OP_I386, I386OP(mov_ax_m16), I386OP(mov_eax_m32), false},
- { 0xA2, OP_I386, I386OP(mov_m8_al), I386OP(mov_m8_al), false},
- { 0xA3, OP_I386, I386OP(mov_m16_ax), I386OP(mov_m32_eax), false},
- { 0xA4, OP_I386, I386OP(movsb), I386OP(movsb), false},
- { 0xA5, OP_I386, I386OP(movsw), I386OP(movsd), false},
- { 0xA6, OP_I386, I386OP(cmpsb), I386OP(cmpsb), false},
- { 0xA7, OP_I386, I386OP(cmpsw), I386OP(cmpsd), false},
- { 0xA8, OP_I386, I386OP(test_al_i8), I386OP(test_al_i8), false},
- { 0xA9, OP_I386, I386OP(test_ax_i16), I386OP(test_eax_i32), false},
- { 0xAA, OP_I386, I386OP(stosb), I386OP(stosb), false},
- { 0xAB, OP_I386, I386OP(stosw), I386OP(stosd), false},
- { 0xAC, OP_I386, I386OP(lodsb), I386OP(lodsb), false},
- { 0xAD, OP_I386, I386OP(lodsw), I386OP(lodsd), false},
- { 0xAE, OP_I386, I386OP(scasb), I386OP(scasb), false},
- { 0xAF, OP_I386, I386OP(scasw), I386OP(scasd), false},
- { 0xB0, OP_I386, I386OP(mov_al_i8), I386OP(mov_al_i8), false},
- { 0xB1, OP_I386, I386OP(mov_cl_i8), I386OP(mov_cl_i8), false},
- { 0xB2, OP_I386, I386OP(mov_dl_i8), I386OP(mov_dl_i8), false},
- { 0xB3, OP_I386, I386OP(mov_bl_i8), I386OP(mov_bl_i8), false},
- { 0xB4, OP_I386, I386OP(mov_ah_i8), I386OP(mov_ah_i8), false},
- { 0xB5, OP_I386, I386OP(mov_ch_i8), I386OP(mov_ch_i8), false},
- { 0xB6, OP_I386, I386OP(mov_dh_i8), I386OP(mov_dh_i8), false},
- { 0xB7, OP_I386, I386OP(mov_bh_i8), I386OP(mov_bh_i8), false},
- { 0xB8, OP_I386, I386OP(mov_ax_i16), I386OP(mov_eax_i32), false},
- { 0xB9, OP_I386, I386OP(mov_cx_i16), I386OP(mov_ecx_i32), false},
- { 0xBA, OP_I386, I386OP(mov_dx_i16), I386OP(mov_edx_i32), false},
- { 0xBB, OP_I386, I386OP(mov_bx_i16), I386OP(mov_ebx_i32), false},
- { 0xBC, OP_I386, I386OP(mov_sp_i16), I386OP(mov_esp_i32), false},
- { 0xBD, OP_I386, I386OP(mov_bp_i16), I386OP(mov_ebp_i32), false},
- { 0xBE, OP_I386, I386OP(mov_si_i16), I386OP(mov_esi_i32), false},
- { 0xBF, OP_I386, I386OP(mov_di_i16), I386OP(mov_edi_i32), false},
- { 0xC0, OP_I386, I386OP(groupC0_8), I386OP(groupC0_8), false},
- { 0xC1, OP_I386, I386OP(groupC1_16), I386OP(groupC1_32), false},
- { 0xC2, OP_I386, I386OP(ret_near16_i16), I386OP(ret_near32_i16), false},
- { 0xC3, OP_I386, I386OP(ret_near16), I386OP(ret_near32), false},
- { 0xC4, OP_I386, I386OP(les16), I386OP(les32), false},
- { 0xC5, OP_I386, I386OP(lds16), I386OP(lds32), false},
- { 0xC6, OP_I386, I386OP(mov_rm8_i8), I386OP(mov_rm8_i8), false},
- { 0xC7, OP_I386, I386OP(mov_rm16_i16), I386OP(mov_rm32_i32), false},
- { 0xC8, OP_I386, I386OP(enter16), I386OP(enter32), false},
- { 0xC9, OP_I386, I386OP(leave16), I386OP(leave32), false},
- { 0xCA, OP_I386, I386OP(retf_i16), I386OP(retf_i32), false},
- { 0xCB, OP_I386, I386OP(retf16), I386OP(retf32), false},
- { 0xCC, OP_I386, I386OP(int3), I386OP(int3), false},
- { 0xCD, OP_I386, I386OP(int), I386OP(int), false},
- { 0xCE, OP_I386, I386OP(into), I386OP(into), false},
- { 0xCF, OP_I386, I386OP(iret16), I386OP(iret32), false},
- { 0xD0, OP_I386, I386OP(groupD0_8), I386OP(groupD0_8), false},
- { 0xD1, OP_I386, I386OP(groupD1_16), I386OP(groupD1_32), false},
- { 0xD2, OP_I386, I386OP(groupD2_8), I386OP(groupD2_8), false},
- { 0xD3, OP_I386, I386OP(groupD3_16), I386OP(groupD3_32), false},
- { 0xD4, OP_I386, I386OP(aam), I386OP(aam), false},
- { 0xD5, OP_I386, I386OP(aad), I386OP(aad), false},
- { 0xD6, OP_I386, I386OP(setalc), I386OP(setalc), false},
- { 0xD7, OP_I386, I386OP(xlat), I386OP(xlat), false},
- { 0xD8, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xD9, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xDA, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xDB, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xDC, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xDD, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xDE, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xDF, OP_I386, I386OP(escape), I386OP(escape), false},
- { 0xD8, OP_FPU, I386OP(x87_group_d8), I386OP(x87_group_d8), false},
- { 0xD9, OP_FPU, I386OP(x87_group_d9), I386OP(x87_group_d9), false},
- { 0xDA, OP_FPU, I386OP(x87_group_da), I386OP(x87_group_da), false},
- { 0xDB, OP_FPU, I386OP(x87_group_db), I386OP(x87_group_db), false},
- { 0xDC, OP_FPU, I386OP(x87_group_dc), I386OP(x87_group_dc), false},
- { 0xDD, OP_FPU, I386OP(x87_group_dd), I386OP(x87_group_dd), false},
- { 0xDE, OP_FPU, I386OP(x87_group_de), I386OP(x87_group_de), false},
- { 0xDF, OP_FPU, I386OP(x87_group_df), I386OP(x87_group_df), false},
- { 0xE0, OP_I386, I386OP(loopne16), I386OP(loopne32), false},
- { 0xE1, OP_I386, I386OP(loopz16), I386OP(loopz32), false},
- { 0xE2, OP_I386, I386OP(loop16), I386OP(loop32), false},
- { 0xE3, OP_I386, I386OP(jcxz16), I386OP(jcxz32), false},
- { 0xE4, OP_I386, I386OP(in_al_i8), I386OP(in_al_i8), false},
- { 0xE5, OP_I386, I386OP(in_ax_i8), I386OP(in_eax_i8), false},
- { 0xE6, OP_I386, I386OP(out_al_i8), I386OP(out_al_i8), false},
- { 0xE7, OP_I386, I386OP(out_ax_i8), I386OP(out_eax_i8), false},
- { 0xE8, OP_I386, I386OP(call_rel16), I386OP(call_rel32), false},
- { 0xE9, OP_I386, I386OP(jmp_rel16), I386OP(jmp_rel32), false},
- { 0xEA, OP_I386, I386OP(jmp_abs16), I386OP(jmp_abs32), false},
- { 0xEB, OP_I386, I386OP(jmp_rel8), I386OP(jmp_rel8), false},
- { 0xEC, OP_I386, I386OP(in_al_dx), I386OP(in_al_dx), false},
- { 0xED, OP_I386, I386OP(in_ax_dx), I386OP(in_eax_dx), false},
- { 0xEE, OP_I386, I386OP(out_al_dx), I386OP(out_al_dx), false},
- { 0xEF, OP_I386, I386OP(out_ax_dx), I386OP(out_eax_dx), false},
- { 0xF0, OP_I386, I386OP(lock), I386OP(lock), false},
- { 0xF1, OP_I386, I386OP(invalid), I386OP(invalid), false},
- { 0xF2, OP_I386, I386OP(repne), I386OP(repne), false},
- { 0xF3, OP_I386, I386OP(rep), I386OP(rep), false},
- { 0xF4, OP_I386, I386OP(hlt), I386OP(hlt), false},
- { 0xF5, OP_I386, I386OP(cmc), I386OP(cmc), false},
- { 0xF6, OP_I386, I386OP(groupF6_8), I386OP(groupF6_8), true },
- { 0xF7, OP_I386, I386OP(groupF7_16), I386OP(groupF7_32), true },
- { 0xF8, OP_I386, I386OP(clc), I386OP(clc), false},
- { 0xF9, OP_I386, I386OP(stc), I386OP(stc), false},
- { 0xFA, OP_I386, I386OP(cli), I386OP(cli), false},
- { 0xFB, OP_I386, I386OP(sti), I386OP(sti), false},
- { 0xFC, OP_I386, I386OP(cld), I386OP(cld), false},
- { 0xFD, OP_I386, I386OP(std), I386OP(std), false},
- { 0xFE, OP_I386, I386OP(groupFE_8), I386OP(groupFE_8), true },
- { 0xFF, OP_I386, I386OP(groupFF_16), I386OP(groupFF_32), true },
- /* 0F ?? */
- { 0x00, OP_2BYTE|OP_I386, I386OP(group0F00_16), I386OP(group0F00_32), false},
- { 0x01, OP_2BYTE|OP_I386, I386OP(group0F01_16), I386OP(group0F01_32), false},
- { 0x01, OP_2BYTE|OP_I486, I486OP(group0F01_16), I486OP(group0F01_32), false},
- { 0x02, OP_2BYTE|OP_I386, I386OP(lar_r16_rm16), I386OP(lar_r32_rm32), false},
- { 0x03, OP_2BYTE|OP_I386, I386OP(lsl_r16_rm16), I386OP(lsl_r32_rm32), false},
- { 0x06, OP_2BYTE|OP_I386, I386OP(clts), I386OP(clts), false},
- { 0x07, OP_2BYTE|OP_I386, I386OP(loadall), I386OP(loadall), false},
- { 0x08, OP_2BYTE|OP_I486, I486OP(invd), I486OP(invd), false},
- { 0x09, OP_2BYTE|OP_I486, I486OP(wbinvd), I486OP(wbinvd), false},
- { 0x0B, OP_2BYTE|OP_PENTIUM, PENTIUMOP(ud2), PENTIUMOP(ud2), false},
- { 0x10, OP_2BYTE|OP_SSE, SSEOP(movups_r128_rm128), SSEOP(movups_r128_rm128), false},
- { 0x11, OP_2BYTE|OP_SSE, SSEOP(movups_rm128_r128), SSEOP(movups_rm128_r128), false},
- { 0x12, OP_2BYTE|OP_SSE, SSEOP(movlps_r128_m64), SSEOP(movlps_r128_m64), false},
- { 0x13, OP_2BYTE|OP_SSE, SSEOP(movlps_m64_r128), SSEOP(movlps_m64_r128), false},
- { 0x14, OP_2BYTE|OP_SSE, SSEOP(unpcklps_r128_rm128), SSEOP(unpcklps_r128_rm128), false},
- { 0x15, OP_2BYTE|OP_SSE, SSEOP(unpckhps_r128_rm128), SSEOP(unpckhps_r128_rm128), false},
- { 0x16, OP_2BYTE|OP_SSE, SSEOP(movhps_r128_m64), SSEOP(movhps_r128_m64), false},
- { 0x17, OP_2BYTE|OP_SSE, SSEOP(movhps_m64_r128), SSEOP(movhps_m64_r128), false},
- { 0x18, OP_2BYTE|OP_PENTIUM, PENTIUMOP(prefetch_m8), PENTIUMOP(prefetch_m8), false},
- { 0x20, OP_2BYTE|OP_I386, I386OP(mov_r32_cr), I386OP(mov_r32_cr), false},
- { 0x21, OP_2BYTE|OP_I386, I386OP(mov_r32_dr), I386OP(mov_r32_dr), false},
- { 0x22, OP_2BYTE|OP_I386, I386OP(mov_cr_r32), I386OP(mov_cr_r32), false},
- { 0x22, OP_2BYTE|OP_I486, I486OP(mov_cr_r32), I486OP(mov_cr_r32), false},
- { 0x23, OP_2BYTE|OP_I386, I386OP(mov_dr_r32), I386OP(mov_dr_r32), false},
- { 0x24, OP_2BYTE|OP_I386, I386OP(mov_r32_tr), I386OP(mov_r32_tr), false},
- { 0x26, OP_2BYTE|OP_I386, I386OP(mov_tr_r32), I386OP(mov_tr_r32), false},
- { 0x28, OP_2BYTE|OP_SSE, SSEOP(movaps_r128_rm128), SSEOP(movaps_r128_rm128), false},
- { 0x29, OP_2BYTE|OP_SSE, SSEOP(movaps_rm128_r128), SSEOP(movaps_rm128_r128), false},
- { 0x2a, OP_2BYTE|OP_SSE, SSEOP(cvtpi2ps_r128_rm64), SSEOP(cvtpi2ps_r128_rm64), false},
- { 0x2b, OP_2BYTE|OP_SSE, SSEOP(movntps_m128_r128), SSEOP(movntps_m128_r128), false},
- { 0x2c, OP_2BYTE|OP_SSE, SSEOP(cvttps2pi_r64_r128m64), SSEOP(cvttps2pi_r64_r128m64),false},
- { 0x2d, OP_2BYTE|OP_SSE, SSEOP(cvtps2pi_r64_r128m64), SSEOP(cvtps2pi_r64_r128m64),false},
- { 0x2e, OP_2BYTE|OP_SSE, SSEOP(ucomiss_r128_r128m32), SSEOP(ucomiss_r128_r128m32),false},
- { 0x2f, OP_2BYTE|OP_SSE, SSEOP(comiss_r128_r128m32), SSEOP(comiss_r128_r128m32), false},
- { 0x30, OP_2BYTE|OP_PENTIUM, PENTIUMOP(wrmsr), PENTIUMOP(wrmsr), false},
- { 0x31, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdtsc), PENTIUMOP(rdtsc), false},
- { 0x32, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rdmsr), PENTIUMOP(rdmsr), false},
- { 0x38, OP_2BYTE|OP_PENTIUM, I386OP(decode_three_byte38), I386OP(decode_three_byte38),false},
- { 0x3A, OP_2BYTE|OP_PENTIUM, I386OP(decode_three_byte3a), I386OP(decode_three_byte3a),false},
- { 0x3A, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
- { 0x3B, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
- { 0x3C, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
- { 0x3D, OP_2BYTE|OP_CYRIX, I386OP(cyrix_special), I386OP(cyrix_special), false},
- { 0x40, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovo_r16_rm16), PENTIUMOP(cmovo_r32_rm32), false},
- { 0x41, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovno_r16_rm16), PENTIUMOP(cmovno_r32_rm32), false},
- { 0x42, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovb_r16_rm16), PENTIUMOP(cmovb_r32_rm32), false},
- { 0x43, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovae_r16_rm16), PENTIUMOP(cmovae_r32_rm32), false},
- { 0x44, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmove_r16_rm16), PENTIUMOP(cmove_r32_rm32), false},
- { 0x45, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovne_r16_rm16), PENTIUMOP(cmovne_r32_rm32), false},
- { 0x46, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovbe_r16_rm16), PENTIUMOP(cmovbe_r32_rm32), false},
- { 0x47, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmova_r16_rm16), PENTIUMOP(cmova_r32_rm32), false},
- { 0x48, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovs_r16_rm16), PENTIUMOP(cmovs_r32_rm32), false},
- { 0x49, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovns_r16_rm16), PENTIUMOP(cmovns_r32_rm32), false},
- { 0x4a, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovp_r16_rm16), PENTIUMOP(cmovp_r32_rm32), false},
- { 0x4b, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovnp_r16_rm16), PENTIUMOP(cmovnp_r32_rm32), false},
- { 0x4c, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovl_r16_rm16), PENTIUMOP(cmovl_r32_rm32), false},
- { 0x4d, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovge_r16_rm16), PENTIUMOP(cmovge_r32_rm32), false},
- { 0x4e, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovle_r16_rm16), PENTIUMOP(cmovle_r32_rm32), false},
- { 0x4f, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmovg_r16_rm16), PENTIUMOP(cmovg_r32_rm32), false},
- { 0x50, OP_2BYTE|OP_SSE, SSEOP(movmskps_r16_r128), SSEOP(movmskps_r32_r128), false},
- { 0x51, OP_2BYTE|OP_SSE, SSEOP(sqrtps_r128_rm128), SSEOP(sqrtps_r128_rm128), false},
- { 0x52, OP_2BYTE|OP_SSE, SSEOP(rsqrtps_r128_rm128), SSEOP(rsqrtps_r128_rm128), false},
- { 0x53, OP_2BYTE|OP_SSE, SSEOP(rcpps_r128_rm128), SSEOP(rcpps_r128_rm128), false},
- { 0x54, OP_2BYTE|OP_SSE, SSEOP(andps_r128_rm128), SSEOP(andps_r128_rm128), false},
- { 0x55, OP_2BYTE|OP_SSE, SSEOP(andnps_r128_rm128), SSEOP(andnps_r128_rm128), false},
- { 0x56, OP_2BYTE|OP_SSE, SSEOP(orps_r128_rm128), SSEOP(orps_r128_rm128), false},
- { 0x57, OP_2BYTE|OP_SSE, SSEOP(xorps), SSEOP(xorps), false},
- { 0x58, OP_2BYTE|OP_SSE, SSEOP(addps), SSEOP(addps), false},
- { 0x59, OP_2BYTE|OP_SSE, SSEOP(mulps), SSEOP(mulps), false},
- { 0x5a, OP_2BYTE|OP_SSE, SSEOP(cvtps2pd_r128_r128m64), SSEOP(cvtps2pd_r128_r128m64),false},
- { 0x5b, OP_2BYTE|OP_SSE, SSEOP(cvtdq2ps_r128_rm128), SSEOP(cvtdq2ps_r128_rm128), false},
- { 0x5c, OP_2BYTE|OP_SSE, SSEOP(subps), SSEOP(subps), false},
- { 0x5d, OP_2BYTE|OP_SSE, SSEOP(minps), SSEOP(minps), false},
- { 0x5e, OP_2BYTE|OP_SSE, SSEOP(divps), SSEOP(divps), false},
- { 0x5f, OP_2BYTE|OP_SSE, SSEOP(maxps), SSEOP(maxps), false},
- { 0x60, OP_2BYTE|OP_MMX, MMXOP(punpcklbw_r64_r64m32), MMXOP(punpcklbw_r64_r64m32),false},
- { 0x61, OP_2BYTE|OP_MMX, MMXOP(punpcklwd_r64_r64m32), MMXOP(punpcklwd_r64_r64m32),false},
- { 0x62, OP_2BYTE|OP_MMX, MMXOP(punpckldq_r64_r64m32), MMXOP(punpckldq_r64_r64m32),false},
- { 0x63, OP_2BYTE|OP_MMX, MMXOP(packsswb_r64_rm64), MMXOP(packsswb_r64_rm64), false},
- { 0x64, OP_2BYTE|OP_MMX, MMXOP(pcmpgtb_r64_rm64), MMXOP(pcmpgtb_r64_rm64), false},
- { 0x65, OP_2BYTE|OP_MMX, MMXOP(pcmpgtw_r64_rm64), MMXOP(pcmpgtw_r64_rm64), false},
- { 0x66, OP_2BYTE|OP_MMX, MMXOP(pcmpgtd_r64_rm64), MMXOP(pcmpgtd_r64_rm64), false},
- { 0x67, OP_2BYTE|OP_MMX, MMXOP(packuswb_r64_rm64), MMXOP(packuswb_r64_rm64), false},
- { 0x68, OP_2BYTE|OP_MMX, MMXOP(punpckhbw_r64_rm64), MMXOP(punpckhbw_r64_rm64), false},
- { 0x69, OP_2BYTE|OP_MMX, MMXOP(punpckhwd_r64_rm64), MMXOP(punpckhwd_r64_rm64), false},
- { 0x6a, OP_2BYTE|OP_MMX, MMXOP(punpckhdq_r64_rm64), MMXOP(punpckhdq_r64_rm64), false},
- { 0x6b, OP_2BYTE|OP_MMX, MMXOP(packssdw_r64_rm64), MMXOP(packssdw_r64_rm64), false},
- { 0x6e, OP_2BYTE|OP_MMX, MMXOP(movd_r64_rm32), MMXOP(movd_r64_rm32), false},
- { 0x6f, OP_2BYTE|OP_MMX, MMXOP(movq_r64_rm64), MMXOP(movq_r64_rm64), false},
- { 0x70, OP_2BYTE|OP_MMX, MMXOP(pshufw_r64_rm64_i8), MMXOP(pshufw_r64_rm64_i8), false},
- { 0x71, OP_2BYTE|OP_MMX, MMXOP(group_0f71), MMXOP(group_0f71), false},
- { 0x72, OP_2BYTE|OP_MMX, MMXOP(group_0f72), MMXOP(group_0f72), false},
- { 0x73, OP_2BYTE|OP_MMX, MMXOP(group_0f73), MMXOP(group_0f73), false},
- { 0x74, OP_2BYTE|OP_CYRIX, I386OP(cyrix_unknown), I386OP(cyrix_unknown), false},
- { 0x74, OP_2BYTE|OP_MMX, MMXOP(pcmpeqb_r64_rm64), MMXOP(pcmpeqb_r64_rm64), false},
- { 0x75, OP_2BYTE|OP_MMX, MMXOP(pcmpeqw_r64_rm64), MMXOP(pcmpeqw_r64_rm64), false},
- { 0x76, OP_2BYTE|OP_MMX, MMXOP(pcmpeqd_r64_rm64), MMXOP(pcmpeqd_r64_rm64), false},
- { 0x77, OP_2BYTE|OP_MMX, MMXOP(emms), MMXOP(emms), false},
- { 0x78, OP_2BYTE|OP_CYRIX, I386OP(cyrix_svdc), I386OP(cyrix_svdc), false},
- { 0x79, OP_2BYTE|OP_CYRIX, I386OP(cyrix_rsdc), I386OP(cyrix_rsdc), false},
- { 0x7a, OP_2BYTE|OP_CYRIX, I386OP(cyrix_svldt), I386OP(cyrix_svldt), false},
- { 0x7b, OP_2BYTE|OP_CYRIX, I386OP(cyrix_rsldt), I386OP(cyrix_rsldt), false},
- { 0x7c, OP_2BYTE|OP_CYRIX, I386OP(cyrix_svts), I386OP(cyrix_svts), false},
- { 0x7d, OP_2BYTE|OP_CYRIX, I386OP(cyrix_rsts), I386OP(cyrix_rsts), false},
- { 0x7e, OP_2BYTE|OP_MMX, MMXOP(movd_rm32_r64), MMXOP(movd_rm32_r64), false},
- { 0x7f, OP_2BYTE|OP_MMX, MMXOP(movq_rm64_r64), MMXOP(movq_rm64_r64), false},
- { 0x80, OP_2BYTE|OP_I386, I386OP(jo_rel16), I386OP(jo_rel32), false},
- { 0x81, OP_2BYTE|OP_I386, I386OP(jno_rel16), I386OP(jno_rel32), false},
- { 0x82, OP_2BYTE|OP_I386, I386OP(jc_rel16), I386OP(jc_rel32), false},
- { 0x83, OP_2BYTE|OP_I386, I386OP(jnc_rel16), I386OP(jnc_rel32), false},
- { 0x84, OP_2BYTE|OP_I386, I386OP(jz_rel16), I386OP(jz_rel32), false},
- { 0x85, OP_2BYTE|OP_I386, I386OP(jnz_rel16), I386OP(jnz_rel32), false},
- { 0x86, OP_2BYTE|OP_I386, I386OP(jbe_rel16), I386OP(jbe_rel32), false},
- { 0x87, OP_2BYTE|OP_I386, I386OP(ja_rel16), I386OP(ja_rel32), false},
- { 0x88, OP_2BYTE|OP_I386, I386OP(js_rel16), I386OP(js_rel32), false},
- { 0x89, OP_2BYTE|OP_I386, I386OP(jns_rel16), I386OP(jns_rel32), false},
- { 0x8A, OP_2BYTE|OP_I386, I386OP(jp_rel16), I386OP(jp_rel32), false},
- { 0x8B, OP_2BYTE|OP_I386, I386OP(jnp_rel16), I386OP(jnp_rel32), false},
- { 0x8C, OP_2BYTE|OP_I386, I386OP(jl_rel16), I386OP(jl_rel32), false},
- { 0x8D, OP_2BYTE|OP_I386, I386OP(jge_rel16), I386OP(jge_rel32), false},
- { 0x8E, OP_2BYTE|OP_I386, I386OP(jle_rel16), I386OP(jle_rel32), false},
- { 0x8F, OP_2BYTE|OP_I386, I386OP(jg_rel16), I386OP(jg_rel32), false},
- { 0x90, OP_2BYTE|OP_I386, I386OP(seto_rm8), I386OP(seto_rm8), false},
- { 0x91, OP_2BYTE|OP_I386, I386OP(setno_rm8), I386OP(setno_rm8), false},
- { 0x92, OP_2BYTE|OP_I386, I386OP(setc_rm8), I386OP(setc_rm8), false},
- { 0x93, OP_2BYTE|OP_I386, I386OP(setnc_rm8), I386OP(setnc_rm8), false},
- { 0x94, OP_2BYTE|OP_I386, I386OP(setz_rm8), I386OP(setz_rm8), false},
- { 0x95, OP_2BYTE|OP_I386, I386OP(setnz_rm8), I386OP(setnz_rm8), false},
- { 0x96, OP_2BYTE|OP_I386, I386OP(setbe_rm8), I386OP(setbe_rm8), false},
- { 0x97, OP_2BYTE|OP_I386, I386OP(seta_rm8), I386OP(seta_rm8), false},
- { 0x98, OP_2BYTE|OP_I386, I386OP(sets_rm8), I386OP(sets_rm8), false},
- { 0x99, OP_2BYTE|OP_I386, I386OP(setns_rm8), I386OP(setns_rm8), false},
- { 0x9A, OP_2BYTE|OP_I386, I386OP(setp_rm8), I386OP(setp_rm8), false},
- { 0x9B, OP_2BYTE|OP_I386, I386OP(setnp_rm8), I386OP(setnp_rm8), false},
- { 0x9C, OP_2BYTE|OP_I386, I386OP(setl_rm8), I386OP(setl_rm8), false},
- { 0x9D, OP_2BYTE|OP_I386, I386OP(setge_rm8), I386OP(setge_rm8), false},
- { 0x9E, OP_2BYTE|OP_I386, I386OP(setle_rm8), I386OP(setle_rm8), false},
- { 0x9F, OP_2BYTE|OP_I386, I386OP(setg_rm8), I386OP(setg_rm8), false},
- { 0xA0, OP_2BYTE|OP_I386, I386OP(push_fs16), I386OP(push_fs32), false},
- { 0xA1, OP_2BYTE|OP_I386, I386OP(pop_fs16), I386OP(pop_fs32), false},
- { 0xA2, OP_2BYTE|OP_I486, I486OP(cpuid), I486OP(cpuid), false},
- { 0xA3, OP_2BYTE|OP_I386, I386OP(bt_rm16_r16), I386OP(bt_rm32_r32), false},
- { 0xA4, OP_2BYTE|OP_I386, I386OP(shld16_i8), I386OP(shld32_i8), false},
- { 0xA5, OP_2BYTE|OP_I386, I386OP(shld16_cl), I386OP(shld32_cl), false},
- { 0xA8, OP_2BYTE|OP_I386, I386OP(push_gs16), I386OP(push_gs32), false},
- { 0xA9, OP_2BYTE|OP_I386, I386OP(pop_gs16), I386OP(pop_gs32), false},
- { 0xAA, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rsm), PENTIUMOP(rsm), false},
- { 0xAB, OP_2BYTE|OP_I386, I386OP(bts_rm16_r16), I386OP(bts_rm32_r32), true },
- { 0xAC, OP_2BYTE|OP_I386, I386OP(shrd16_i8), I386OP(shrd32_i8), false},
- { 0xAD, OP_2BYTE|OP_I386, I386OP(shrd16_cl), I386OP(shrd32_cl), false},
- { 0xAE, OP_2BYTE|OP_SSE, SSEOP(group_0fae), SSEOP(group_0fae), false},
- { 0xAF, OP_2BYTE|OP_I386, I386OP(imul_r16_rm16), I386OP(imul_r32_rm32), false},
- { 0xB0, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm8_r8), I486OP(cmpxchg_rm8_r8), true },
- { 0xB1, OP_2BYTE|OP_I486, I486OP(cmpxchg_rm16_r16), I486OP(cmpxchg_rm32_r32), true },
- { 0xB2, OP_2BYTE|OP_I386, I386OP(lss16), I386OP(lss32), false},
- { 0xB3, OP_2BYTE|OP_I386, I386OP(btr_rm16_r16), I386OP(btr_rm32_r32), true },
- { 0xB4, OP_2BYTE|OP_I386, I386OP(lfs16), I386OP(lfs32), false},
- { 0xB5, OP_2BYTE|OP_I386, I386OP(lgs16), I386OP(lgs32), false},
- { 0xB6, OP_2BYTE|OP_I386, I386OP(movzx_r16_rm8), I386OP(movzx_r32_rm8), false},
- { 0xB7, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movzx_r32_rm16), false},
- { 0xBA, OP_2BYTE|OP_I386, I386OP(group0FBA_16), I386OP(group0FBA_32), true },
- { 0xBB, OP_2BYTE|OP_I386, I386OP(btc_rm16_r16), I386OP(btc_rm32_r32), true },
- { 0xBC, OP_2BYTE|OP_I386, I386OP(bsf_r16_rm16), I386OP(bsf_r32_rm32), false},
- { 0xBD, OP_2BYTE|OP_I386, I386OP(bsr_r16_rm16), I386OP(bsr_r32_rm32), false},
- { 0xBE, OP_2BYTE|OP_I386, I386OP(movsx_r16_rm8), I386OP(movsx_r32_rm8), false},
- { 0xBF, OP_2BYTE|OP_I386, I386OP(invalid), I386OP(movsx_r32_rm16), false},
- { 0xC0, OP_2BYTE|OP_I486, I486OP(xadd_rm8_r8), I486OP(xadd_rm8_r8), true },
- { 0xC1, OP_2BYTE|OP_I486, I486OP(xadd_rm16_r16), I486OP(xadd_rm32_r32), true },
- { 0xC2, OP_2BYTE|OP_SSE, SSEOP(cmpps_r128_rm128_i8), SSEOP(cmpps_r128_rm128_i8), false},
- { 0xC3, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movnti_m16_r16), PENTIUMOP(movnti_m32_r32), false},
- { 0xC4, OP_2BYTE|OP_SSE, SSEOP(pinsrw_r64_r16m16_i8), SSEOP(pinsrw_r64_r32m16_i8),false},
- { 0xC5, OP_2BYTE|OP_SSE, SSEOP(pextrw_r16_r64_i8), SSEOP(pextrw_r32_r64_i8), false},
- { 0xC6, OP_2BYTE|OP_SSE, SSEOP(shufps), SSEOP(shufps), false},
- { 0xC7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(cmpxchg8b_m64), PENTIUMOP(cmpxchg8b_m64), true },
- { 0xC8, OP_2BYTE|OP_I486, I486OP(bswap_eax), I486OP(bswap_eax), false},
- { 0xC9, OP_2BYTE|OP_I486, I486OP(bswap_ecx), I486OP(bswap_ecx), false},
- { 0xCA, OP_2BYTE|OP_I486, I486OP(bswap_edx), I486OP(bswap_edx), false},
- { 0xCB, OP_2BYTE|OP_I486, I486OP(bswap_ebx), I486OP(bswap_ebx), false},
- { 0xCC, OP_2BYTE|OP_I486, I486OP(bswap_esp), I486OP(bswap_esp), false},
- { 0xCD, OP_2BYTE|OP_I486, I486OP(bswap_ebp), I486OP(bswap_ebp), false},
- { 0xCE, OP_2BYTE|OP_I486, I486OP(bswap_esi), I486OP(bswap_esi), false},
- { 0xCF, OP_2BYTE|OP_I486, I486OP(bswap_edi), I486OP(bswap_edi), false},
- { 0xD1, OP_2BYTE|OP_MMX, MMXOP(psrlw_r64_rm64), MMXOP(psrlw_r64_rm64), false},
- { 0xD2, OP_2BYTE|OP_MMX, MMXOP(psrld_r64_rm64), MMXOP(psrld_r64_rm64), false},
- { 0xD3, OP_2BYTE|OP_MMX, MMXOP(psrlq_r64_rm64), MMXOP(psrlq_r64_rm64), false},
- { 0xD4, OP_2BYTE|OP_MMX, MMXOP(paddq_r64_rm64), MMXOP(paddq_r64_rm64), false},
- { 0xD5, OP_2BYTE|OP_MMX, MMXOP(pmullw_r64_rm64), MMXOP(pmullw_r64_rm64), false},
- { 0xD7, OP_2BYTE|OP_SSE, SSEOP(pmovmskb_r16_r64), SSEOP(pmovmskb_r32_r64), false},
- { 0xD8, OP_2BYTE|OP_MMX, MMXOP(psubusb_r64_rm64), MMXOP(psubusb_r64_rm64), false},
- { 0xD9, OP_2BYTE|OP_MMX, MMXOP(psubusw_r64_rm64), MMXOP(psubusw_r64_rm64), false},
- { 0xDA, OP_2BYTE|OP_SSE, SSEOP(pminub_r64_rm64), SSEOP(pminub_r64_rm64), false},
- { 0xDB, OP_2BYTE|OP_MMX, MMXOP(pand_r64_rm64), MMXOP(pand_r64_rm64), false},
- { 0xDC, OP_2BYTE|OP_MMX, MMXOP(paddusb_r64_rm64), MMXOP(paddusb_r64_rm64), false},
- { 0xDD, OP_2BYTE|OP_MMX, MMXOP(paddusw_r64_rm64), MMXOP(paddusw_r64_rm64), false},
- { 0xDE, OP_2BYTE|OP_SSE, SSEOP(pmaxub_r64_rm64), SSEOP(pmaxub_r64_rm64), false},
- { 0xDF, OP_2BYTE|OP_MMX, MMXOP(pandn_r64_rm64), MMXOP(pandn_r64_rm64), false},
- { 0xE0, OP_2BYTE|OP_SSE, SSEOP(pavgb_r64_rm64), SSEOP(pavgb_r64_rm64), false},
- { 0xE1, OP_2BYTE|OP_MMX, MMXOP(psraw_r64_rm64), MMXOP(psraw_r64_rm64), false},
- { 0xE2, OP_2BYTE|OP_MMX, MMXOP(psrad_r64_rm64), MMXOP(psrad_r64_rm64), false},
- { 0xE3, OP_2BYTE|OP_SSE, SSEOP(pavgw_r64_rm64), SSEOP(pavgw_r64_rm64), false},
- { 0xE4, OP_2BYTE|OP_SSE, SSEOP(pmulhuw_r64_rm64), SSEOP(pmulhuw_r64_rm64), false},
- { 0xE5, OP_2BYTE|OP_MMX, MMXOP(pmulhw_r64_rm64), MMXOP(pmulhw_r64_rm64), false},
- { 0xE7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(movntq_m64_r64), PENTIUMOP(movntq_m64_r64), false},
- { 0xE8, OP_2BYTE|OP_MMX, MMXOP(psubsb_r64_rm64), MMXOP(psubsb_r64_rm64), false},
- { 0xE9, OP_2BYTE|OP_MMX, MMXOP(psubsw_r64_rm64), MMXOP(psubsw_r64_rm64), false},
- { 0xEA, OP_2BYTE|OP_SSE, SSEOP(pminsw_r64_rm64), SSEOP(pminsw_r64_rm64), false},
- { 0xEB, OP_2BYTE|OP_MMX, MMXOP(por_r64_rm64), MMXOP(por_r64_rm64), false},
- { 0xEC, OP_2BYTE|OP_MMX, MMXOP(paddsb_r64_rm64), MMXOP(paddsb_r64_rm64), false},
- { 0xED, OP_2BYTE|OP_MMX, MMXOP(paddsw_r64_rm64), MMXOP(paddsw_r64_rm64), false},
- { 0xEE, OP_2BYTE|OP_SSE, SSEOP(pmaxsw_r64_rm64), SSEOP(pmaxsw_r64_rm64), false},
- { 0xEF, OP_2BYTE|OP_MMX, MMXOP(pxor_r64_rm64), MMXOP(pxor_r64_rm64), false},
- { 0xF1, OP_2BYTE|OP_MMX, MMXOP(psllw_r64_rm64), MMXOP(psllw_r64_rm64), false},
- { 0xF2, OP_2BYTE|OP_MMX, MMXOP(pslld_r64_rm64), MMXOP(pslld_r64_rm64), false},
- { 0xF3, OP_2BYTE|OP_MMX, MMXOP(psllq_r64_rm64), MMXOP(psllq_r64_rm64), false},
- { 0xF4, OP_2BYTE|OP_SSE, SSEOP(pmuludq_r64_rm64), SSEOP(pmuludq_r64_rm64), false},
- { 0xF5, OP_2BYTE|OP_MMX, MMXOP(pmaddwd_r64_rm64), MMXOP(pmaddwd_r64_rm64), false},
- { 0xF6, OP_2BYTE|OP_SSE, SSEOP(psadbw_r64_rm64), SSEOP(psadbw_r64_rm64), false},
- { 0xf7, OP_2BYTE|OP_PENTIUM, PENTIUMOP(maskmovq_r64_r64), PENTIUMOP(maskmovq_r64_r64),false},
- { 0xF8, OP_2BYTE|OP_MMX, MMXOP(psubb_r64_rm64), MMXOP(psubb_r64_rm64), false},
- { 0xF9, OP_2BYTE|OP_MMX, MMXOP(psubw_r64_rm64), MMXOP(psubw_r64_rm64), false},
- { 0xFA, OP_2BYTE|OP_MMX, MMXOP(psubd_r64_rm64), MMXOP(psubd_r64_rm64), false},
- { 0xFB, OP_2BYTE|OP_SSE, SSEOP(psubq_r64_rm64), SSEOP(psubq_r64_rm64), false},
- { 0xFC, OP_2BYTE|OP_MMX, MMXOP(paddb_r64_rm64), MMXOP(paddb_r64_rm64), false},
- { 0xFD, OP_2BYTE|OP_MMX, MMXOP(paddw_r64_rm64), MMXOP(paddw_r64_rm64), false},
- { 0xFE, OP_2BYTE|OP_MMX, MMXOP(paddd_r64_rm64), MMXOP(paddd_r64_rm64), false},
- /* F3 0F ?? */
- { 0x10, OP_3BYTEF3|OP_SSE, SSEOP(movss_r128_rm128), SSEOP(movss_r128_rm128), false},
- { 0x11, OP_3BYTEF3|OP_SSE, SSEOP(movss_rm128_r128), SSEOP(movss_rm128_r128), false},
- { 0x12, OP_3BYTEF3|OP_SSE, SSEOP(movsldup_r128_rm128), SSEOP(movsldup_r128_rm128), false},
- { 0x16, OP_3BYTEF3|OP_SSE, SSEOP(movshdup_r128_rm128), SSEOP(movshdup_r128_rm128), false},
- { 0x2A, OP_3BYTEF3|OP_SSE, SSEOP(cvtsi2ss_r128_rm32), SSEOP(cvtsi2ss_r128_rm32), false},
- { 0x2C, OP_3BYTEF3|OP_SSE, SSEOP(cvttss2si_r32_r128m32), SSEOP(cvttss2si_r32_r128m32),false},
- { 0x2D, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2si_r32_r128m32), SSEOP(cvtss2si_r32_r128m32),false},
- { 0x51, OP_3BYTEF3|OP_SSE, SSEOP(sqrtss_r128_r128m32), SSEOP(sqrtss_r128_r128m32), false},
- { 0x52, OP_3BYTEF3|OP_SSE, SSEOP(rsqrtss_r128_r128m32), SSEOP(rsqrtss_r128_r128m32),false},
- { 0x53, OP_3BYTEF3|OP_SSE, SSEOP(rcpss_r128_r128m32), SSEOP(rcpss_r128_r128m32), false},
- { 0x58, OP_3BYTEF3|OP_SSE, SSEOP(addss), SSEOP(addss), false},
- { 0x59, OP_3BYTEF3|OP_SSE, SSEOP(mulss), SSEOP(mulss), false},
- { 0x5A, OP_3BYTEF3|OP_SSE, SSEOP(cvtss2sd_r128_r128m32), SSEOP(cvtss2sd_r128_r128m32),false},
- { 0x5B, OP_3BYTEF3|OP_SSE, SSEOP(cvttps2dq_r128_rm128), SSEOP(cvttps2dq_r128_rm128),false},
- { 0x5C, OP_3BYTEF3|OP_SSE, SSEOP(subss), SSEOP(subss), false},
- { 0x5D, OP_3BYTEF3|OP_SSE, SSEOP(minss_r128_r128m32), SSEOP(minss_r128_r128m32), false},
- { 0x5E, OP_3BYTEF3|OP_SSE, SSEOP(divss), SSEOP(divss), false},
- { 0x5F, OP_3BYTEF3|OP_SSE, SSEOP(maxss_r128_r128m32), SSEOP(maxss_r128_r128m32), false},
- { 0x6F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_r128_rm128), SSEOP(movdqu_r128_rm128), false},
- { 0x70, OP_3BYTEF3|OP_SSE, SSEOP(pshufhw_r128_rm128_i8), SSEOP(pshufhw_r128_rm128_i8),false},
- { 0x7E, OP_3BYTEF3|OP_SSE, SSEOP(movq_r128_r128m64), SSEOP(movq_r128_r128m64), false},
- { 0x7F, OP_3BYTEF3|OP_SSE, SSEOP(movdqu_rm128_r128), SSEOP(movdqu_rm128_r128), false},
- { 0xAE, OP_3BYTE66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xB8, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(popcnt_r16_rm16), PENTIUMOP(popcnt_r32_rm32), false},
- { 0xBC, OP_3BYTEF3|OP_PENTIUM, PENTIUMOP(tzcnt_r16_rm16), PENTIUMOP(tzcnt_r32_rm32), false},
- { 0xC2, OP_3BYTEF3|OP_SSE, SSEOP(cmpss_r128_r128m32_i8), SSEOP(cmpss_r128_r128m32_i8),false},
- { 0xC7, OP_3BYTEF2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xD6, OP_3BYTEF3|OP_SSE, SSEOP(movq2dq_r128_r64), SSEOP(movq2dq_r128_r64), false},
- { 0xE6, OP_3BYTEF3|OP_SSE, SSEOP(cvtdq2pd_r128_r128m64), SSEOP(cvtdq2pd_r128_r128m64),false},
- /* F2 0F ?? */
- { 0x10, OP_3BYTEF2|OP_SSE, SSEOP(movsd_r128_r128m64), SSEOP(movsd_r128_r128m64), false},
- { 0x11, OP_3BYTEF2|OP_SSE, SSEOP(movsd_r128m64_r128), SSEOP(movsd_r128m64_r128), false},
- { 0x12, OP_3BYTEF2|OP_SSE, SSEOP(movddup_r128_r128m64), SSEOP(movddup_r128_r128m64),false},
- { 0x2A, OP_3BYTEF2|OP_SSE, SSEOP(cvtsi2sd_r128_rm32), SSEOP(cvtsi2sd_r128_rm32), false},
- { 0x2C, OP_3BYTEF2|OP_SSE, SSEOP(cvttsd2si_r32_r128m64), SSEOP(cvttsd2si_r32_r128m64),false},
- { 0x2D, OP_3BYTEF2|OP_SSE, SSEOP(cvtsd2si_r32_r128m64), SSEOP(cvtsd2si_r32_r128m64),false},
- { 0x51, OP_3BYTEF2|OP_SSE, SSEOP(sqrtsd_r128_r128m64), SSEOP(sqrtsd_r128_r128m64), false},
- { 0x58, OP_3BYTEF2|OP_SSE, SSEOP(addsd_r128_r128m64), SSEOP(addsd_r128_r128m64), false},
- { 0x59, OP_3BYTEF2|OP_SSE, SSEOP(mulsd_r128_r128m64), SSEOP(mulsd_r128_r128m64), false},
- { 0x5A, OP_3BYTEF2|OP_SSE, SSEOP(cvtsd2ss_r128_r128m64), SSEOP(cvtsd2ss_r128_r128m64),false},
- { 0x5C, OP_3BYTEF2|OP_SSE, SSEOP(subsd_r128_r128m64), SSEOP(subsd_r128_r128m64), false},
- { 0x5D, OP_3BYTEF2|OP_SSE, SSEOP(minsd_r128_r128m64), SSEOP(minsd_r128_r128m64), false},
- { 0x5E, OP_3BYTEF2|OP_SSE, SSEOP(divsd_r128_r128m64), SSEOP(divsd_r128_r128m64), false},
- { 0x5F, OP_3BYTEF2|OP_SSE, SSEOP(maxsd_r128_r128m64), SSEOP(maxsd_r128_r128m64), false},
- { 0x70, OP_3BYTEF2|OP_SSE, SSEOP(pshuflw_r128_rm128_i8), SSEOP(pshuflw_r128_rm128_i8),false},
- { 0x7C, OP_3BYTEF2|OP_SSE, SSEOP(haddps_r128_rm128), SSEOP(haddps_r128_rm128), false},
- { 0x7D, OP_3BYTEF2|OP_SSE, SSEOP(hsubps_r128_rm128), SSEOP(hsubps_r128_rm128), false},
- { 0xC2, OP_3BYTEF2|OP_SSE, SSEOP(cmpsd_r128_r128m64_i8), SSEOP(cmpsd_r128_r128m64_i8),false},
- { 0xD0, OP_3BYTEF2|OP_SSE, SSEOP(addsubps_r128_rm128), SSEOP(addsubps_r128_rm128), false},
- { 0xD6, OP_3BYTEF2|OP_SSE, SSEOP(movdq2q_r64_r128), SSEOP(movdq2q_r64_r128), false},
- { 0xE6, OP_3BYTEF2|OP_SSE, SSEOP(cvtpd2dq_r128_rm128), SSEOP(cvtpd2dq_r128_rm128), false},
- { 0xF0, OP_3BYTEF2|OP_SSE, SSEOP(lddqu_r128_m128), SSEOP(lddqu_r128_m128), false},
- /* 66 0F ?? */
- { 0x10, OP_3BYTE66|OP_SSE, SSEOP(movupd_r128_rm128), SSEOP(movupd_r128_rm128), false},
- { 0x11, OP_3BYTE66|OP_SSE, SSEOP(movupd_rm128_r128), SSEOP(movupd_rm128_r128), false},
- { 0x12, OP_3BYTE66|OP_SSE, SSEOP(movlpd_r128_m64), SSEOP(movlpd_r128_m64), false},
- { 0x13, OP_3BYTE66|OP_SSE, SSEOP(movlpd_m64_r128), SSEOP(movlpd_m64_r128), false},
- { 0x14, OP_3BYTE66|OP_SSE, SSEOP(unpcklpd_r128_rm128), SSEOP(unpcklpd_r128_rm128), false},
- { 0x15, OP_3BYTE66|OP_SSE, SSEOP(unpckhpd_r128_rm128), SSEOP(unpckhpd_r128_rm128), false},
- { 0x16, OP_3BYTE66|OP_SSE, SSEOP(movhpd_r128_m64), SSEOP(movhpd_r128_m64), false},
- { 0x17, OP_3BYTE66|OP_SSE, SSEOP(movhpd_m64_r128), SSEOP(movhpd_m64_r128), false},
- { 0x28, OP_3BYTE66|OP_SSE, SSEOP(movapd_r128_rm128), SSEOP(movapd_r128_rm128), false},
- { 0x29, OP_3BYTE66|OP_SSE, SSEOP(movapd_rm128_r128), SSEOP(movapd_rm128_r128), false},
- { 0x2A, OP_3BYTE66|OP_SSE, SSEOP(cvtpi2pd_r128_rm64), SSEOP(cvtpi2pd_r128_rm64), false},
- { 0x2B, OP_3BYTE66|OP_SSE, SSEOP(movntpd_m128_r128), SSEOP(movntpd_m128_r128), false},
- { 0x2C, OP_3BYTE66|OP_SSE, SSEOP(cvttpd2pi_r64_rm128), SSEOP(cvttpd2pi_r64_rm128), false},
- { 0x2D, OP_3BYTE66|OP_SSE, SSEOP(cvtpd2pi_r64_rm128), SSEOP(cvtpd2pi_r64_rm128), false},
- { 0x2E, OP_3BYTE66|OP_SSE, SSEOP(ucomisd_r128_r128m64), SSEOP(ucomisd_r128_r128m64),false},
- { 0x2F, OP_3BYTE66|OP_SSE, SSEOP(comisd_r128_r128m64), SSEOP(comisd_r128_r128m64), false},
- { 0x50, OP_3BYTE66|OP_SSE, SSEOP(movmskpd_r32_r128), SSEOP(movmskpd_r32_r128), false},
- { 0x51, OP_3BYTE66|OP_SSE, SSEOP(sqrtpd_r128_rm128), SSEOP(sqrtpd_r128_rm128), false},
- { 0x54, OP_3BYTE66|OP_SSE, SSEOP(andpd_r128_rm128), SSEOP(andpd_r128_rm128), false},
- { 0x55, OP_3BYTE66|OP_SSE, SSEOP(andnpd_r128_rm128), SSEOP(andnpd_r128_rm128), false},
- { 0x56, OP_3BYTE66|OP_SSE, SSEOP(orpd_r128_rm128), SSEOP(orpd_r128_rm128), false},
- { 0x57, OP_3BYTE66|OP_SSE, SSEOP(xorpd_r128_rm128), SSEOP(xorpd_r128_rm128), false},
- { 0x58, OP_3BYTE66|OP_SSE, SSEOP(addpd_r128_rm128), SSEOP(addpd_r128_rm128), false},
- { 0x59, OP_3BYTE66|OP_SSE, SSEOP(mulpd_r128_rm128), SSEOP(mulpd_r128_rm128), false},
- { 0x5A, OP_3BYTE66|OP_SSE, SSEOP(cvtpd2ps_r128_rm128), SSEOP(cvtpd2ps_r128_rm128), false},
- { 0x5B, OP_3BYTE66|OP_SSE, SSEOP(cvtps2dq_r128_rm128), SSEOP(cvtps2dq_r128_rm128), false},
- { 0x5C, OP_3BYTE66|OP_SSE, SSEOP(subpd_r128_rm128), SSEOP(subpd_r128_rm128), false},
- { 0x5D, OP_3BYTE66|OP_SSE, SSEOP(minpd_r128_rm128), SSEOP(minpd_r128_rm128), false},
- { 0x5E, OP_3BYTE66|OP_SSE, SSEOP(divpd_r128_rm128), SSEOP(divpd_r128_rm128), false},
- { 0x5F, OP_3BYTE66|OP_SSE, SSEOP(maxpd_r128_rm128), SSEOP(maxpd_r128_rm128), false},
- { 0x60, OP_3BYTE66|OP_SSE, SSEOP(punpcklbw_r128_rm128), SSEOP(punpcklbw_r128_rm128),false},
- { 0x61, OP_3BYTE66|OP_SSE, SSEOP(punpcklwd_r128_rm128), SSEOP(punpcklwd_r128_rm128),false},
- { 0x62, OP_3BYTE66|OP_SSE, SSEOP(punpckldq_r128_rm128), SSEOP(punpckldq_r128_rm128),false},
- { 0x63, OP_3BYTE66|OP_SSE, SSEOP(packsswb_r128_rm128), SSEOP(packsswb_r128_rm128), false},
- { 0x64, OP_3BYTE66|OP_SSE, SSEOP(pcmpgtb_r128_rm128), SSEOP(pcmpgtb_r128_rm128), false},
- { 0x65, OP_3BYTE66|OP_SSE, SSEOP(pcmpgtw_r128_rm128), SSEOP(pcmpgtw_r128_rm128), false},
- { 0x66, OP_3BYTE66|OP_SSE, SSEOP(pcmpgtd_r128_rm128), SSEOP(pcmpgtd_r128_rm128), false},
- { 0x67, OP_3BYTE66|OP_SSE, SSEOP(packuswb_r128_rm128), SSEOP(packuswb_r128_rm128), false},
- { 0x68, OP_3BYTE66|OP_SSE, SSEOP(punpckhbw_r128_rm128), SSEOP(punpckhbw_r128_rm128),false},
- { 0x69, OP_3BYTE66|OP_SSE, SSEOP(punpckhwd_r128_rm128), SSEOP(punpckhwd_r128_rm128),false},
- { 0x6A, OP_3BYTE66|OP_SSE, SSEOP(unpckhdq_r128_rm128), SSEOP(unpckhdq_r128_rm128), false},
- { 0x6B, OP_3BYTE66|OP_SSE, SSEOP(packssdw_r128_rm128), SSEOP(packssdw_r128_rm128), false},
- { 0x6C, OP_3BYTE66|OP_SSE, SSEOP(punpcklqdq_r128_rm128), SSEOP(punpcklqdq_r128_rm128),false},
- { 0x6D, OP_3BYTE66|OP_SSE, SSEOP(punpckhqdq_r128_rm128), SSEOP(punpckhqdq_r128_rm128),false},
- { 0x6E, OP_3BYTE66|OP_SSE, SSEOP(movd_m128_rm32), SSEOP(movd_m128_rm32), false},
- { 0x6F, OP_3BYTE66|OP_SSE, SSEOP(movdqa_m128_rm128), SSEOP(movdqa_m128_rm128), false},
- { 0x70, OP_3BYTE66|OP_SSE, SSEOP(pshufd_r128_rm128_i8), SSEOP(pshufd_r128_rm128_i8),false},
- { 0x71, OP_3BYTE66|OP_SSE, SSEOP(group_660f71), SSEOP(group_660f71), false},
- { 0x72, OP_3BYTE66|OP_SSE, SSEOP(group_660f72), SSEOP(group_660f72), false},
- { 0x73, OP_3BYTE66|OP_SSE, SSEOP(group_660f73), SSEOP(group_660f73), false},
- { 0x74, OP_3BYTE66|OP_SSE, SSEOP(pcmpeqb_r128_rm128), SSEOP(pcmpeqb_r128_rm128), false},
- { 0x75, OP_3BYTE66|OP_SSE, SSEOP(pcmpeqw_r128_rm128), SSEOP(pcmpeqw_r128_rm128), false},
- { 0x76, OP_3BYTE66|OP_SSE, SSEOP(pcmpeqd_r128_rm128), SSEOP(pcmpeqd_r128_rm128), false},
- { 0x7C, OP_3BYTE66|OP_SSE, SSEOP(haddpd_r128_rm128), SSEOP(haddpd_r128_rm128), false},
- { 0x7D, OP_3BYTE66|OP_SSE, SSEOP(hsubpd_r128_rm128), SSEOP(hsubpd_r128_rm128), false},
- { 0x7E, OP_3BYTE66|OP_SSE, SSEOP(movd_rm32_r128), SSEOP(movd_rm32_r128), false},
- { 0x7F, OP_3BYTE66|OP_SSE, SSEOP(movdqa_rm128_r128), SSEOP(movdqa_rm128_r128), false},
- { 0xC2, OP_3BYTE66|OP_SSE, SSEOP(cmppd_r128_rm128_i8), SSEOP(cmppd_r128_rm128_i8), false},
- { 0xC4, OP_3BYTE66|OP_SSE, SSEOP(pinsrw_r128_r32m16_i8), SSEOP(pinsrw_r128_r32m16_i8),false},
- { 0xC5, OP_3BYTE66|OP_SSE, SSEOP(pextrw_reg_r128_i8), SSEOP(pextrw_reg_r128_i8), false},
- { 0xC6, OP_3BYTE66|OP_SSE, SSEOP(shufpd_r128_rm128_i8), SSEOP(shufpd_r128_rm128_i8),false},
- { 0xC7, OP_3BYTE66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xD0, OP_3BYTE66|OP_SSE, SSEOP(addsubpd_r128_rm128), SSEOP(addsubpd_r128_rm128), false},
- { 0xD1, OP_3BYTE66|OP_SSE, SSEOP(psrlw_r128_rm128), SSEOP(psrlw_r128_rm128), false},
- { 0xD2, OP_3BYTE66|OP_SSE, SSEOP(psrld_r128_rm128), SSEOP(psrld_r128_rm128), false},
- { 0xD3, OP_3BYTE66|OP_SSE, SSEOP(psrlq_r128_rm128), SSEOP(psrlq_r128_rm128), false},
- { 0xD4, OP_3BYTE66|OP_SSE, SSEOP(paddq_r128_rm128), SSEOP(paddq_r128_rm128), false},
- { 0xD5, OP_3BYTE66|OP_SSE, SSEOP(pmullw_r128_rm128), SSEOP(pmullw_r128_rm128), false},
- { 0xD6, OP_3BYTE66|OP_SSE, SSEOP(movq_r128m64_r128), SSEOP(movq_r128m64_r128), false},
- { 0xD7, OP_3BYTE66|OP_SSE, SSEOP(pmovmskb_r32_r128), SSEOP(pmovmskb_r32_r128), false},
- { 0xD8, OP_3BYTE66|OP_SSE, SSEOP(psubusb_r128_rm128), SSEOP(psubusb_r128_rm128), false},
- { 0xD9, OP_3BYTE66|OP_SSE, SSEOP(psubusw_r128_rm128), SSEOP(psubusw_r128_rm128), false},
- { 0xDA, OP_3BYTE66|OP_SSE, SSEOP(pminub_r128_rm128), SSEOP(pminub_r128_rm128), false},
- { 0xDB, OP_3BYTE66|OP_SSE, SSEOP(pand_r128_rm128), SSEOP(pand_r128_rm128), false},
- { 0xDC, OP_3BYTE66|OP_SSE, SSEOP(paddusb_r128_rm128), SSEOP(paddusb_r128_rm128), false},
- { 0xDD, OP_3BYTE66|OP_SSE, SSEOP(paddusw_r128_rm128), SSEOP(paddusw_r128_rm128), false},
- { 0xDE, OP_3BYTE66|OP_SSE, SSEOP(pmaxub_r128_rm128), SSEOP(pmaxub_r128_rm128), false},
- { 0xDF, OP_3BYTE66|OP_SSE, SSEOP(pandn_r128_rm128), SSEOP(pandn_r128_rm128), false},
- { 0xE0, OP_3BYTE66|OP_SSE, SSEOP(pavgb_r128_rm128), SSEOP(pavgb_r128_rm128), false},
- { 0xE1, OP_3BYTE66|OP_SSE, SSEOP(psraw_r128_rm128), SSEOP(psraw_r128_rm128), false},
- { 0xE2, OP_3BYTE66|OP_SSE, SSEOP(psrad_r128_rm128), SSEOP(psrad_r128_rm128), false},
- { 0xE3, OP_3BYTE66|OP_SSE, SSEOP(pavgw_r128_rm128), SSEOP(pavgw_r128_rm128), false},
- { 0xE4, OP_3BYTE66|OP_SSE, SSEOP(pmulhuw_r128_rm128), SSEOP(pmulhuw_r128_rm128), false},
- { 0xE5, OP_3BYTE66|OP_SSE, SSEOP(pmulhw_r128_rm128), SSEOP(pmulhw_r128_rm128), false},
- { 0xE6, OP_3BYTE66|OP_SSE, SSEOP(cvttpd2dq_r128_rm128), SSEOP(cvttpd2dq_r128_rm128),false},
- { 0xE7, OP_3BYTE66|OP_SSE, SSEOP(movntdq_m128_r128), SSEOP(movntdq_m128_r128), false},
- { 0xE8, OP_3BYTE66|OP_SSE, SSEOP(psubsb_r128_rm128), SSEOP(psubsb_r128_rm128), false},
- { 0xE9, OP_3BYTE66|OP_SSE, SSEOP(psubsw_r128_rm128), SSEOP(psubsw_r128_rm128), false},
- { 0xEA, OP_3BYTE66|OP_SSE, SSEOP(pminsw_r128_rm128), SSEOP(pminsw_r128_rm128), false},
- { 0xEB, OP_3BYTE66|OP_SSE, SSEOP(por_r128_rm128), SSEOP(por_r128_rm128), false},
- { 0xEC, OP_3BYTE66|OP_SSE, SSEOP(paddsb_r128_rm128), SSEOP(paddsb_r128_rm128), false},
- { 0xED, OP_3BYTE66|OP_SSE, SSEOP(paddsw_r128_rm128), SSEOP(paddsw_r128_rm128), false},
- { 0xEE, OP_3BYTE66|OP_SSE, SSEOP(pmaxsw_r128_rm128), SSEOP(pmaxsw_r128_rm128), false},
- { 0xEF, OP_3BYTE66|OP_SSE, SSEOP(pxor_r128_rm128), SSEOP(pxor_r128_rm128), false},
- { 0xF1, OP_3BYTE66|OP_SSE, SSEOP(psllw_r128_rm128), SSEOP(psllw_r128_rm128), false},
- { 0xF2, OP_3BYTE66|OP_SSE, SSEOP(pslld_r128_rm128), SSEOP(pslld_r128_rm128), false},
- { 0xF3, OP_3BYTE66|OP_SSE, SSEOP(psllq_r128_rm128), SSEOP(psllq_r128_rm128), false},
- { 0xF4, OP_3BYTE66|OP_SSE, SSEOP(pmuludq_r128_rm128), SSEOP(pmuludq_r128_rm128), false},
- { 0xF5, OP_3BYTE66|OP_SSE, SSEOP(pmaddwd_r128_rm128), SSEOP(pmaddwd_r128_rm128), false},
- { 0xF6, OP_3BYTE66|OP_SSE, SSEOP(psadbw_r128_rm128), SSEOP(psadbw_r128_rm128), false},
- { 0xF7, OP_3BYTE66|OP_SSE, SSEOP(maskmovdqu_r128_r128), SSEOP(maskmovdqu_r128_r128),false},
- { 0xF8, OP_3BYTE66|OP_SSE, SSEOP(psubb_r128_rm128), SSEOP(psubb_r128_rm128), false},
- { 0xF9, OP_3BYTE66|OP_SSE, SSEOP(psubw_r128_rm128), SSEOP(psubw_r128_rm128), false},
- { 0xFA, OP_3BYTE66|OP_SSE, SSEOP(psubd_r128_rm128), SSEOP(psubd_r128_rm128), false},
- { 0xFB, OP_3BYTE66|OP_SSE, SSEOP(psubq_r128_rm128), SSEOP(psubq_r128_rm128), false},
- { 0xFC, OP_3BYTE66|OP_SSE, SSEOP(paddb_r128_rm128), SSEOP(paddb_r128_rm128), false},
- { 0xFD, OP_3BYTE66|OP_SSE, SSEOP(paddw_r128_rm128), SSEOP(paddw_r128_rm128), false},
- { 0xFE, OP_3BYTE66|OP_SSE, SSEOP(paddd_r128_rm128), SSEOP(paddd_r128_rm128), false},
- /* 0F 38 ?? */
- { 0x00, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x01, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x02, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x03, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x04, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x05, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x06, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x07, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x08, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x09, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0A, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0B, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1C, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1D, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1E, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF0, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF1, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF2, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF3, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF5, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF7, OP_3BYTE38|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- /* 0F 3A ?? */
- { 0x0F, OP_3BYTE3A|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- /* 66 0F 38 ?? */
- { 0x00, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x01, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x02, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x03, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x04, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x05, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x06, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x07, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x08, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x09, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x10, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x13, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x14, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x15, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x16, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x17, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x18, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x19, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x20, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x21, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x22, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x23, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x24, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x25, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x28, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x29, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x2A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x2B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x2C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x2D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x2E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x2F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x30, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x31, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x32, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x33, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x34, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x35, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x36, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x37, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x38, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x39, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x3A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x3B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x3C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x3D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x3E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x3F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x40, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x41, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x45, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x46, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x47, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x58, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x59, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x5A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x78, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x79, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x80, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x81, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x82, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x8C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x8E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x90, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x91, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x92, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x93, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x96, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x97, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x98, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x99, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x9A, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x9B, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x9C, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x9D, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x9E, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x9F, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xA6, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xA7, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xA8, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xA9, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xAA, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xAB, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xAC, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xAD, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xAE, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xAF, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xB6, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xB7, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xB8, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xB9, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xBA, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xBB, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xBC, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xBD, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xBE, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xBF, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xDB, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xDC, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xDD, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xDE, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xDF, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF0, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF1, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF3, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF6, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF7, OP_4BYTE3866|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- /* F2 0F 38 ?? */
- { 0xF0, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF1, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF3, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF5, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF6, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF7, OP_4BYTE38F2|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- /* F3 0F 38 ?? */
- { 0xF3, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF5, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF6, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xF7, OP_4BYTE38F3|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- /* 66 0F 3A ?? */
- { 0x00, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x01, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x02, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x04, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x05, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x06, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x08, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x09, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0A, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0B, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0C, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0D, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0E, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x0F, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x14, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x15, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x16, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x17, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x18, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x19, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x1D, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x20, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x21, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x22, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x38, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x39, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x40, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x41, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x42, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x44, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x46, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x4A, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x4B, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x4C, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x60, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x61, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x62, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0x63, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- { 0xDF, OP_4BYTE3A66|OP_SSE, I386OP(invalid), I386OP(invalid), false},
- /* F2 0F 3A ?? */
- { 0xF0, OP_4BYTE3AF2|OP_SSE, I386OP(invalid), I386OP(invalid), false}
-};
DEVICE *pic;
DEVICE *program;
DEVICE *io;
+#ifdef I386_PSEUDO_BIOS
DEVICE *bios;
-
+#endif
+#ifdef SINGLE_MODE_DMA
DEVICE *dma;
-
-//#ifdef USE_DEBUGGER
+#endif
+#ifdef USE_DEBUGGER
EMU *emu;
DEBUGGER *debugger;
DEVICE *program_stored;
DEVICE *io_stored;
-//#endif
+#endif
UINT32 a20_mask;
int cpuid_max_input_value_eax;
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