Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner' into...

* clk-aspeed:
  clk: aspeed: Handle inverse polarity of USB port 1 clock gate
  clk: aspeed: Fix return value check in aspeed_cc_init()
  clk: aspeed: Add reset controller
  clk: aspeed: Register gated clocks
  clk: aspeed: Add platform driver and register PLLs
  clk: aspeed: Register core clocks
  clk: Add clock driver for ASPEED BMC SoCs
  dt-bindings: clock: Add ASPEED constants

* clk-lock-UP:
  clk: fix reentrancy of clk_enable() on UP systems

* clk-mediatek:
  clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built
  clk: mediatek: Fix all warnings for missing struct clk_onecell_data
  clk: mediatek: fixup test-building of MediaTek clock drivers
  clk: mediatek: group drivers under indpendent menu

* clk-allwinner:
  clk: sunxi-ng: a83t: Add M divider to TCON1 clock
  clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
  clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
  dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
  clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
  clk: sunxi-ng: Support fixed post-dividers on NM style clocks
  clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
  clk: sunxi-ng: Support fixed post-dividers on MP style clocks
  clk: sunxi: Use PTR_ERR_OR_ZERO()

diff --cc drivers/clk/Kconfig
Simple merge

diff --cc drivers/clk/Makefile
Simple merge

diff --cc drivers/clk/clk.c
index 32867dd,647d056,b221d80,647d056,647d056..98f89cc
--- 1/drivers/clk/clk.c
--- 2/drivers/clk/clk.c
--- 3/drivers/clk/clk.c
--- 4/drivers/clk/clk.c
--- 5/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@@@@@ -1078,58 -934,15 -942,15 -934,15 -934,15 +1086,58 @@@@@@ static int clk_core_determine_round_nol
                        return rate;
     
                req->rate = rate;
 ----   } else if (core->flags & CLK_SET_RATE_PARENT) {
 ----           return clk_core_round_rate_nolock(parent, req);
        } else {
 ----           req->rate = core->rate;
 ++++           return -EINVAL;
 + ++   }
 + ++
 + ++   return 0;
 + ++}
 + ++
 ++++static void clk_core_init_rate_req(struct clk_core * const core,
 ++++                              struct clk_rate_request *req)
 ++++{
 ++++   struct clk_core *parent;
 ++++
 ++++   if (WARN_ON(!core || !req))
 ++++           return;
 ++++
 ++++   parent = core->parent;
 ++++   if (parent) {
 ++++           req->best_parent_hw = parent->hw;
 ++++           req->best_parent_rate = parent->rate;
 ++++   } else {
 ++++           req->best_parent_hw = NULL;
 ++++           req->best_parent_rate = 0;
  +     }
 ++++}
 ++++
 ++++static bool clk_core_can_round(struct clk_core * const core)
 ++++{
 ++++   if (core->ops->determine_rate || core->ops->round_rate)
 ++++           return true;
 ++++
 ++++   return false;
 ++++}
 ++++
 ++++static int clk_core_round_rate_nolock(struct clk_core *core,
 ++++                                 struct clk_rate_request *req)
 ++++{
 ++++   lockdep_assert_held(&prepare_lock);
  +  
 ++++   if (!core)
 ++++           return 0;
 ++++
 ++++   clk_core_init_rate_req(core, req);
 ++++
 ++++   if (clk_core_can_round(core))
 ++++           return clk_core_determine_round_nolock(core, req);
 ++++   else if (core->flags & CLK_SET_RATE_PARENT)
 ++++           return clk_core_round_rate_nolock(core->parent, req);
 ++++
 ++++   req->rate = core->rate;
  +     return 0;
  +  }
  +  
     /**
      * __clk_determine_rate - get the closest rate actually supported by a clock
      * @hw: determine the rate of this clock