{
if(!(sub_run)) {
printf("SUB HALT\n");
- if(halt_count == 0) subcpu->write_signal(SIG_CPU_BUSREQ, 0x01, 0x01);
+ //if(halt_count == 0) subcpu->write_signal(SIG_CPU_BUSREQ, 0x01, 0x01);
+ subcpu->write_signal(SIG_CPU_BUSREQ, 0x01, 0x01);
halt_count++;
}
if(halt_count >= 0x7ffffff0) halt_count = 0x7ffffff0;
void DISPLAY::go_subcpu(void)
{
- if((sub_run) && (halt_count > 0)) {
+ if((sub_run)) {
printf("SUB RUN\n");
halt_count--;
- if(halt_count == 0) subcpu->write_signal(SIG_CPU_BUSREQ, 0x00, 0x01);
+ //if(halt_count == 0) subcpu->write_signal(SIG_CPU_BUSREQ, 0x00, 0x01);
+ subcpu->write_signal(SIG_CPU_BUSREQ, 0x00, 0x01);
}
if(halt_count < 0) halt_count = 0;
}
void DISPLAY::halt_subsystem(void)
{
- halt_flag = false;
- sub_run = false;
- if(halt_event_id >= 0) cancel_event(this, halt_event_id);
- register_event_by_clock(this, EVENT_FM7SUB_HALT, 10, true, &halt_event_id);
- //mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x00, 0x01);
+ sub_run = false;
+ mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x00, 0x01);
+ halt_subcpu();
}
void DISPLAY::restart_subsystem(void)
{
sub_run = true;
- halt_flag = false;
- if(sub_run) {
- if(halt_event_id >= 0) cancel_event(this, halt_event_id);
- halt_event_id = -1;
- go_subcpu();
- mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x01, 0x01); // BUSY
- }
-// go_subcpu();
-// mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x01, 0x01); // BUSY
+ go_subcpu();
}
//SUB:D408:R
uint8 DISPLAY::acknowledge_irq(void)
{
this->do_irq(false);
- //mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x00, 0x01);
+ mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x01, 0x01);
return 0xff;
}
switch(event_id) {
case EVENT_FM7SUB_DISPLAY_NMI: // per 20.00ms
do_nmi(true);
- register_event(this, EVENT_FM7SUB_DISPLAY_NMI_OFF, 10.0 * 1000.0, false, NULL); // NEXT CYCLE_
+ register_event_by_clock(this, EVENT_FM7SUB_DISPLAY_NMI_OFF, 100, false, NULL); // NEXT CYCLE_
break;
case EVENT_FM7SUB_DISPLAY_NMI_OFF: // per 20.00ms
do_nmi(false);
register_event(this, EVENT_FM7SUB_VSTART, usec, false, &vstart_event_id); // NEXT CYCLE_
break;
case EVENT_FM7SUB_HALT:
- if(!sub_run) {
- halt_subcpu();
- mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x01, 0x01); // BUSY
- cancel_event(this, halt_event_id);
- halt_event_id = -1;
- halt_flag = true;
- }
+ //if(!sub_run) {
+ //halt_subcpu();
+ //mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0x01, 0x01); // BUSY
+ //cancel_event(this, halt_event_id);
+ //halt_event_id = -1;
+ //halt_flag = true;
+ //}
break;
}
}
{
bool flag = ((data & mask) != 0);
switch(id) {
- case SIG_DISPLAY_HALT:
case SIG_FM7_SUB_HALT:
+ halt_flag = flag;
+ mainio->write_signal(FM7_MAINIO_SUB_BUSY, flag ? 1 : 1, 0x01);
+ break;
+ case SIG_DISPLAY_HALT:
if(flag) {
if(sub_run) halt_subsystem();
} else {
- if(sub_run) return;
+ //if(sub_run) return;
restart_subsystem();
if(subcpu_resetreq) {
vram_wrote = true;
display->set_context_mainio(mainio);
display->set_context_subcpu(subcpu);
display->set_context_keyboard(keyboard);
+ subcpu->set_context_bus_halt(display, SIG_FM7_SUB_HALT, 0xffffffff);
+
display->set_context_kanjiclass1(kanjiclass1);
#if defined(_FM77AV40) || defined(_FM77AV40EX) || defined(_FM77AV40SX)
display->set_context_kanjiclass2(kanjiclass2);
mainmem->set_context_mainio(mainio);
mainmem->set_context_display(display);
+ subcpu->set_context_bus_halt(mainmem, SIG_FM7_SUB_HALT, 0xffffffff);
maincpu->set_context_mem(mainmem);
subcpu->set_context_mem(display);
// FD05
sub_busy = false;
extdet_neg = false;
- sub_haltreq = false;
sub_cancel = false; // bit6 : '1' Cancel req.
switch(config.sound_device_type) {
void FM7_MAINIO::set_fd05(uint8 val)
{
- display->write_signal(SIG_FM7_SUB_HALT, val, 0b10000000);
+ subcpu->write_signal(SIG_CPU_BUSREQ, val, 0b10000000);
+// display->write_signal(SIG_DISPLAY_HALT, val, 0b10000000);
display->write_signal(SIG_FM7_SUB_CANCEL, val, 0b01000000);
- if((val & 0b10000000) == 0) {
- sub_haltreq = false;
- } else {
- sub_haltreq = true;
- }
#ifdef WITH_Z80
if((val & 0b00000001) != 0) {
maincpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
bool sub_busy; // bit7 : '0' = READY '1' = BUSY.
bool extdet_neg; // bit0 : '1' = none , '0' = exists.
/* FD05 : W */
- bool sub_haltreq; // bit7 : '1' = HALT, maybe dummy.
bool sub_cancel; // bit6 : '1' Cancel req.
bool z80_sel; // bit0 : '1' = Z80. Maybe only FM-7/77.
// FD05
sub_busy = false;
extdet_neg = false;
- sub_haltreq = false;
- sub_cancel = false; // bit6 : '1' Cancel req.
z80_sel = false; // bit0 : '1' = Z80. Maybe only FM-7/77.
// FD06,07
intstat_syndet = false;
return nonmmr_convert(addr, realaddr);
}
+void FM7_MAINMEM::write_signal(int sigid, uint32 data, uint32 mask)
+{
+ bool flag = ((data & mask) != 0);
+ switch(sigid) {
+ case SIG_FM7_SUB_HALT:
+ sub_halted = flag;
+ break;
+ }
+}
+
+
uint32 FM7_MAINMEM::read_data8(uint32 addr)
{
uint32 ret;
if(bank < 0) return 0xff; // Illegal
if(bank == FM7_MAINMEM_SHAREDRAM) {
- if(display->read_signal(SIG_DISPLAY_HALT) != 0) return 0xff; // Not halt
+ if(!sub_halted) return 0xff; // Not halt
return display->read_data8(realaddr + 0xd380); // Okay?
} else if(bank == FM7_MAINMEM_MMIO) {
return mainio->read_data8(realaddr);
}
#if defined(_FM77AV_VARIANTS)
else if(bank == FM7_MAINMEM_77AV_DIRECTACCESS) {
- if(display->read_signal(SIG_DISPLAY_HALT) != 0) return 0xff; // Not halt
+ if(!sub_halted) return 0xff; // Not halt
return display->read_data8(realaddr); // Okay?
}
#endif
if(bank < 0) return; // Illegal
if(bank == FM7_MAINMEM_SHAREDRAM) {
- if(display->read_signal(SIG_DISPLAY_HALT) != 0) return; // Not halt
+ if(!sub_halted) return; // Not halt
display->write_data8(realaddr + 0xd380, data); // Okay?
return;
} else if(bank == FM7_MAINMEM_MMIO) {
}
#if defined(_FM77AV_VARIANTS)
else if(bank == FM7_MAINMEM_77AV_DIRECTACCESS) {
- if(display->read_signal(SIG_DISPLAY_HALT) != 0) return; // Not halt
+ if(!sub_halted) return; // Not halt
display->write_data8(realaddr, data); // Okay?
return;
}
waitfactor = 2;
waitcount = 0;
ioaccess_wait = false;
-
+ sub_halted = false;
+
// Initialize table
// $0000-$7FFF
memset(read_table, 0x00, sizeof(read_table));
bool ioaccess_wait;
int waitfactor;
int waitcount;
+ bool sub_halted;
protected:
EMU *p_emu;
VM *p_vm;
write_table[i].memory = NULL;
}
+ void write_signal(int sigid, uint32 data, uint32 mask);
};
#endif