drm/i915/display/adl_p: Implement Wa_16011303918

PSR2 is not compatible with DC3CO or VRR in this stepping, so not
enabling PSR2 if VRR will be enabled or not enabling DC3CO if PSR2 is
possible.

BSpec: 54369
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210616203158.118111-5-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3cb8758..9643624 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -733,6 +733,10 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
        if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
                return;
 
+       /* Wa_16011303918:adlp */
+       if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
+               return;
+
        /*
         * DC3CO Exit time 200us B.Spec 49196
         * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
@@ -961,6 +965,14 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
                return false;
        }
 
+       /* Wa_16011303918:adlp */
+       if (crtc_state->vrr.enable &&
+           IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) {
+               drm_dbg_kms(&dev_priv->drm,
+                           "PSR2 not enabled, not compatible with HW stepping + VRR\n");
+               return false;
+       }
+
        tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
        return true;
 }