+++ /dev/null
--- megafunction wizard: %ALTPLL%\r
--- GENERATION: STANDARD\r
--- VERSION: WM1.0\r
--- MODULE: altpll \r
-\r
--- ============================================================\r
--- File Name: pll_clk_gen.vhd\r
--- Megafunction Name(s):\r
--- altpll\r
---\r
--- Simulation Library Files(s):\r
--- altera_mf\r
--- ============================================================\r
--- ************************************************************\r
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
---\r
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition\r
--- ************************************************************\r
-\r
-\r
---Copyright (C) 1991-2013 Altera Corporation\r
---Your use of Altera Corporation's design tools, logic functions \r
---and other software and tools, and its AMPP partner logic \r
---functions, and any output files from any of the foregoing \r
---(including device programming or simulation files), and any \r
---associated documentation or information are expressly subject \r
---to the terms and conditions of the Altera Program License \r
---Subscription Agreement, Altera MegaCore Function License \r
---Agreement, or other applicable license agreement, including, \r
---without limitation, that your use is for the sole purpose of \r
---programming logic devices manufactured by Altera and sold by \r
---Altera or its authorized distributors. Please refer to the \r
---applicable agreement for further details.\r
-\r
-\r
-LIBRARY ieee;\r
-USE ieee.std_logic_1164.all;\r
-\r
-LIBRARY altera_mf;\r
-USE altera_mf.all;\r
-\r
-ENTITY pll_clk_gen IS\r
- PORT\r
- (\r
- inclk0 : IN STD_LOGIC := '0';\r
- c0 : OUT STD_LOGIC ;\r
- locked : OUT STD_LOGIC \r
- );\r
-END pll_clk_gen;\r
-\r
-\r
-ARCHITECTURE SYN OF pll_clk_gen IS\r
-\r
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);\r
- SIGNAL sub_wire1 : STD_LOGIC ;\r
- SIGNAL sub_wire2 : STD_LOGIC ;\r
- SIGNAL sub_wire3 : STD_LOGIC ;\r
- SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);\r
- SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);\r
- SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);\r
-\r
-\r
-\r
- COMPONENT altpll\r
- GENERIC (\r
- clk0_divide_by : NATURAL;\r
- clk0_duty_cycle : NATURAL;\r
- clk0_multiply_by : NATURAL;\r
- clk0_phase_shift : STRING;\r
- compensate_clock : STRING;\r
- gate_lock_signal : STRING;\r
- inclk0_input_frequency : NATURAL;\r
- intended_device_family : STRING;\r
- invalid_lock_multiplier : NATURAL;\r
- lpm_hint : STRING;\r
- lpm_type : STRING;\r
- operation_mode : STRING;\r
- port_activeclock : STRING;\r
- port_areset : STRING;\r
- port_clkbad0 : STRING;\r
- port_clkbad1 : STRING;\r
- port_clkloss : STRING;\r
- port_clkswitch : STRING;\r
- port_configupdate : STRING;\r
- port_fbin : STRING;\r
- port_inclk0 : STRING;\r
- port_inclk1 : STRING;\r
- port_locked : STRING;\r
- port_pfdena : STRING;\r
- port_phasecounterselect : STRING;\r
- port_phasedone : STRING;\r
- port_phasestep : STRING;\r
- port_phaseupdown : STRING;\r
- port_pllena : STRING;\r
- port_scanaclr : STRING;\r
- port_scanclk : STRING;\r
- port_scanclkena : STRING;\r
- port_scandata : STRING;\r
- port_scandataout : STRING;\r
- port_scandone : STRING;\r
- port_scanread : STRING;\r
- port_scanwrite : STRING;\r
- port_clk0 : STRING;\r
- port_clk1 : STRING;\r
- port_clk2 : STRING;\r
- port_clk3 : STRING;\r
- port_clk4 : STRING;\r
- port_clk5 : STRING;\r
- port_clkena0 : STRING;\r
- port_clkena1 : STRING;\r
- port_clkena2 : STRING;\r
- port_clkena3 : STRING;\r
- port_clkena4 : STRING;\r
- port_clkena5 : STRING;\r
- port_extclk0 : STRING;\r
- port_extclk1 : STRING;\r
- port_extclk2 : STRING;\r
- port_extclk3 : STRING;\r
- valid_lock_multiplier : NATURAL\r
- );\r
- PORT (\r
- clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);\r
- inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);\r
- locked : OUT STD_LOGIC \r
- );\r
- END COMPONENT;\r
-\r
-BEGIN\r
- sub_wire5_bv(0 DOWNTO 0) <= "0";\r
- sub_wire5 <= To_stdlogicvector(sub_wire5_bv);\r
- sub_wire1 <= sub_wire0(0);\r
- c0 <= sub_wire1;\r
- locked <= sub_wire2;\r
- sub_wire3 <= inclk0;\r
- sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;\r
-\r
- altpll_component : altpll\r
- GENERIC MAP (\r
- clk0_divide_by => 250,\r
- clk0_duty_cycle => 50,\r
- clk0_multiply_by => 833,\r
- clk0_phase_shift => "0",\r
- compensate_clock => "CLK0",\r
- gate_lock_signal => "NO",\r
- inclk0_input_frequency => 20000,\r
- intended_device_family => "Cyclone II",\r
- invalid_lock_multiplier => 5,\r
- lpm_hint => "CBX_MODULE_PREFIX=pll_clk_gen",\r
- lpm_type => "altpll",\r
- operation_mode => "NORMAL",\r
- port_activeclock => "PORT_UNUSED",\r
- port_areset => "PORT_UNUSED",\r
- port_clkbad0 => "PORT_UNUSED",\r
- port_clkbad1 => "PORT_UNUSED",\r
- port_clkloss => "PORT_UNUSED",\r
- port_clkswitch => "PORT_UNUSED",\r
- port_configupdate => "PORT_UNUSED",\r
- port_fbin => "PORT_UNUSED",\r
- port_inclk0 => "PORT_USED",\r
- port_inclk1 => "PORT_UNUSED",\r
- port_locked => "PORT_USED",\r
- port_pfdena => "PORT_UNUSED",\r
- port_phasecounterselect => "PORT_UNUSED",\r
- port_phasedone => "PORT_UNUSED",\r
- port_phasestep => "PORT_UNUSED",\r
- port_phaseupdown => "PORT_UNUSED",\r
- port_pllena => "PORT_UNUSED",\r
- port_scanaclr => "PORT_UNUSED",\r
- port_scanclk => "PORT_UNUSED",\r
- port_scanclkena => "PORT_UNUSED",\r
- port_scandata => "PORT_UNUSED",\r
- port_scandataout => "PORT_UNUSED",\r
- port_scandone => "PORT_UNUSED",\r
- port_scanread => "PORT_UNUSED",\r
- port_scanwrite => "PORT_UNUSED",\r
- port_clk0 => "PORT_USED",\r
- port_clk1 => "PORT_UNUSED",\r
- port_clk2 => "PORT_UNUSED",\r
- port_clk3 => "PORT_UNUSED",\r
- port_clk4 => "PORT_UNUSED",\r
- port_clk5 => "PORT_UNUSED",\r
- port_clkena0 => "PORT_UNUSED",\r
- port_clkena1 => "PORT_UNUSED",\r
- port_clkena2 => "PORT_UNUSED",\r
- port_clkena3 => "PORT_UNUSED",\r
- port_clkena4 => "PORT_UNUSED",\r
- port_clkena5 => "PORT_UNUSED",\r
- port_extclk0 => "PORT_UNUSED",\r
- port_extclk1 => "PORT_UNUSED",\r
- port_extclk2 => "PORT_UNUSED",\r
- port_extclk3 => "PORT_UNUSED",\r
- valid_lock_multiplier => 1\r
- )\r
- PORT MAP (\r
- inclk => sub_wire4,\r
- clk => sub_wire0,\r
- locked => sub_wire2\r
- );\r
-\r
-\r
-\r
-END SYN;\r
-\r
--- ============================================================\r
--- CNX file retrieval info\r
--- ============================================================\r
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"\r
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"\r
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"\r
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"\r
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"\r
--- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"\r
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"\r
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"\r
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"\r
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"\r
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"\r
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"\r
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "166.600006"\r
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"\r
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"\r
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"\r
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"\r
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"\r
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"\r
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"\r
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"\r
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"\r
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"\r
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"\r
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"\r
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"\r
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"\r
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"\r
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"\r
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "166.60000000"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"\r
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"\r
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
--- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"\r
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"\r
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"\r
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"\r
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"\r
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_clk_gen.mif"\r
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"\r
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"\r
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"\r
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"\r
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"\r
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"\r
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"\r
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"\r
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"\r
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"\r
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"\r
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "250"\r
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "833"\r
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
--- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"\r
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"\r
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"\r
--- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"\r
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"\r
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"\r
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"\r
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"\r
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"\r
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"\r
--- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"\r
--- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"\r
--- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"\r
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"\r
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"\r
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"\r
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"\r
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0\r
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_clk_gen.vhd TRUE\r
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_clk_gen.ppf TRUE\r
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_clk_gen.inc FALSE\r
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_clk_gen.cmp TRUE\r
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_clk_gen.bsf FALSE\r
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_clk_gen_inst.vhd FALSE\r
--- Retrieval info: LIB_FILE: altera_mf\r
--- Retrieval info: CBX_MODULE_PREFIX: ON\r
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