[InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31)

Multiplying INT_MIN by 1 doesn't trigger nsw.  However, shifting 1 into
the sign bit *does* trigger nsw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235250 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index 35513f1..a554e9f 100644 (file)
--- a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -217,12 +217,16 @@ Instruction *InstCombiner::visitMul(BinaryOperator &I) {
         NewCst = getLogBase2Vector(CV);
 
       if (NewCst) {
+        unsigned Width = NewCst->getType()->getPrimitiveSizeInBits();
         BinaryOperator *Shl = BinaryOperator::CreateShl(NewOp, NewCst);
 
         if (I.hasNoUnsignedWrap())
           Shl->setHasNoUnsignedWrap();
-        if (I.hasNoSignedWrap() && NewCst->isNotMinSignedValue())
-          Shl->setHasNoSignedWrap();
+        if (I.hasNoSignedWrap()) {
+          uint64_t V;
+          if (match(NewCst, m_ConstantInt(V)) && V != Width - 1)
+            Shl->setHasNoSignedWrap();
+        }
 
         return Shl;
       }

diff --git a/test/Transforms/InstCombine/mul.ll b/test/Transforms/InstCombine/mul.ll
index de09f12..6e67c7f 100644 (file)
--- a/test/Transforms/InstCombine/mul.ll
+++ b/test/Transforms/InstCombine/mul.ll
@@ -288,3 +288,19 @@ define i32 @test31(i32 %V) {
 ; CHECK:      %[[mul:.*]] = shl i32 %V, zext (i1 icmp ne (i32* inttoptr (i64 1 to i32*), i32* @PR22087) to i32)
 ; CHECK-NEXT: ret i32 %[[mul]]
 }
+
+define i32 @test32(i32 %X) {
+; CHECK-LABEL: @test32
+  %mul = mul nsw i32 %X, -2147483648
+  ret i32 %mul
+; CHECK:      %[[shl:.*]] = shl i32 %X, 31
+; CHECK-NEXT: ret i32 %[[shl]]
+}
+
+define i32 @test33(i32 %X) {
+; CHECK-LABEL: @test33
+  %mul = mul nsw i32 %X, 1073741824
+; CHECK:      %[[shl:.*]] = shl nsw i32 %X, 30
+; CHECK-NEXT: ret i32 %[[shl]]
+  ret i32 %mul
+}