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drm/amdgpu/soc15: fix xclk for raven
author
Alex Deucher
<alexander.deucher@amd.com>
Wed, 12 Feb 2020 06:46:16 +0000
(
01:46
-0500)
committer
Alex Deucher
<alexander.deucher@amd.com>
Fri, 14 Feb 2020 17:58:58 +0000
(12:58 -0500)
It's 25 Mhz (refclk / 4). This fixes the interpretation
of the rlc clock counter.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/amdgpu/soc15.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index
15f3424
..
2b488df
100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/
drivers/gpu/drm/amd/amdgpu/soc15.c
@@
-272,7
+272,12
@@
static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
static u32 soc15_get_xclk(struct amdgpu_device *adev)
{
- return adev->clock.spll.reference_freq;
+ u32 reference_clock = adev->clock.spll.reference_freq;
+
+ if (adev->asic_type == CHIP_RAVEN)
+ return reference_clock / 4;
+
+ return reference_clock;
}