{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
}
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+ register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
}
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+ register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+ register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
cpu->cfg.epmp = true;
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+ register_cpu_props(DEVICE(obj));
set_priv_version(env, PRIV_VERSION_1_10_0);
cpu->cfg.mmu = false;
}
DEFINE_PROP_END_OF_LIST(),
};
+/*
+ * Register CPU props based on env.misa_ext. If a non-zero
+ * value was set, register only the required cpu->cfg.ext_*
+ * properties and leave. env.misa_ext = 0 means that we want
+ * all the default properties to be registered.
+ */
static void register_cpu_props(DeviceState *dev)
{
+ RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
+ uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
+ /*
+ * If misa_ext is not zero, set cfg properties now to
+ * allow them to be read during riscv_cpu_realize()
+ * later on.
+ */
+ if (cpu->env.misa_ext != 0) {
+ cpu->cfg.ext_i = misa_ext & RVI;
+ cpu->cfg.ext_e = misa_ext & RVE;
+ cpu->cfg.ext_m = misa_ext & RVM;
+ cpu->cfg.ext_a = misa_ext & RVA;
+ cpu->cfg.ext_f = misa_ext & RVF;
+ cpu->cfg.ext_d = misa_ext & RVD;
+ cpu->cfg.ext_v = misa_ext & RVV;
+ cpu->cfg.ext_c = misa_ext & RVC;
+ cpu->cfg.ext_s = misa_ext & RVS;
+ cpu->cfg.ext_u = misa_ext & RVU;
+ cpu->cfg.ext_h = misa_ext & RVH;
+ cpu->cfg.ext_j = misa_ext & RVJ;
+
+ /*
+ * We don't want to set the default riscv_cpu_extensions
+ * in this case.
+ */
+ return;
+ }
+
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
qdev_property_add_static(dev, prop);
}