gas/testsuite/

	* gas/arm/blx-bad.s: New.
	* gas/arm/blx-bad.d: New.

	opcodes/
	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b8ad2c3..a558102 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
+
+       * gas/arm/blx-bad.s: New.
+       * gas/arm/blx-bad.d: New.
+
 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 
        * gas/i386/bmi-intel.d: New.

diff --git a/gas/testsuite/gas/arm/blx-bad.d b/gas/testsuite/gas/arm/blx-bad.d
new file mode 100644 (file)
index 0000000..34f70cc
--- /dev/null
+++ b/gas/testsuite/gas/arm/blx-bad.d
@@ -0,0 +1,21 @@
+#objdump: -drw --show-raw-insn
+#name: BLX encoding
+
+.*:     file format .*arm.*
+
+
+Disassembly of section .text:
+
+00000000 <ARM>:
+   0:  e1a00000        nop                     ; \(mov r0, r0\)
+
+00000004 <THUMB>:
+   4:  f7ff effc       blx     0 <ARM>
+   8:  46c0            nop                     ; \(mov r8, r8\)
+   a:  f7ff effa       blx     0 <ARM>
+   e:  46c0            nop                     ; \(mov r8, r8\)
+  10:  f7ff eff6       blx     0 <ARM>
+  14:  f7ff eff5                       ; <UNDEFINED> instruction: 0xf7ffeff5
+  18:  46c0            nop                     ; \(mov r8, r8\)
+  1a:  f7ff eff1                       ; <UNDEFINED> instruction: 0xf7ffeff1
+  1e:  f7ff eff0       blx     0 <ARM>

diff --git a/gas/testsuite/gas/arm/blx-bad.s b/gas/testsuite/gas/arm/blx-bad.s
new file mode 100644 (file)
index 0000000..cbc9c53
--- /dev/null
+++ b/gas/testsuite/gas/arm/blx-bad.s
@@ -0,0 +1,16 @@
+       .arm
+       .func ARM
+ARM:   nop
+
+       .thumb
+       .thumb_func
+THUMB:
+       blx     ARM
+       nop
+       blx     ARM
+       nop
+       .inst   0xf7ffeff6
+       .inst   0xf7ffeff5
+       nop
+       .inst   0xf7ffeff1
+       .inst   0xf7ffeff0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5284ba4..2083200 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
+
+       * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
+
 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (REG_VEX_38F3): New.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b8d02e5..91eba51 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1563,7 +1563,7 @@ static const struct opcode32 thumb32_opcodes[] =
   {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
 
   /* These have been 32-bit since the invention of Thumb.  */
-  {ARM_EXT_V4T,  0xf000c000, 0xf800d000, "blx%c\t%B%x"},
+  {ARM_EXT_V4T,  0xf000c000, 0xf800d001, "blx%c\t%B%x"},
   {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
 
   /* Fallback.  */