((mir->next->dalvikInsn.opCode == OP_MOVE_RESULT) ||
(mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_OBJECT))) {
mir->next->dalvikInsn.opCode = OP_NOP;
- return getDestLoc(cUnit, mir->next, 0);
+ return dvmCompilerGetDest(cUnit, mir->next, 0);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL;
res.fp = fpHint;
if (mir->next &&
(mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_WIDE)) {
mir->next->dalvikInsn.opCode = OP_NOP;
- return getDestLocWide(cUnit, mir->next, 0, 1);
+ return dvmCompilerGetDestWide(cUnit, mir->next, 0, 1);
} else {
RegLocation res = LOC_DALVIK_RETURN_VAL_WIDE;
res.fp = fpHint;
ArmLIR *pcrLabel)
{
/* Forget all def info (because we might rollback here. Bug #2367397 */
- resetDefTracking(cUnit);
+ dvmCompilerResetDefTracking(cUnit);
/* Set up the place holder to reconstruct this Dalvik PC */
if (pcrLabel == NULL) {
*/
RegLocation rlSrc;
RegLocation rlDest;
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
if (srcSize == 1) {
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
loadValueDirectFixed(cUnit, rlSrc, r0);
} else {
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
loadValueDirectWideFixed(cUnit, rlSrc, r0, r1);
}
loadConstant(cUnit, r2, (int)funct);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (tgtSize == 1) {
RegLocation rlResult;
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = getReturnLoc(cUnit);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
} else {
RegLocation rlResult;
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = getReturnLocWide(cUnit);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
}
return false;
default:
return true;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadValueDirectFixed(cUnit, rlSrc1, r0);
loadValueDirectFixed(cUnit, rlSrc2, r1);
loadConstant(cUnit, r2, (int)funct);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
- rlResult = getReturnLoc(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
return false;
}
default:
return true;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadConstant(cUnit, rlr, (int)funct);
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
opReg(cUnit, kOpBlx, rlr);
- clobberCallRegs(cUnit);
- rlResult = getReturnLocWide(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
return false;
}
static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
RegLocation rlResult;
rlObj = loadValue(cUnit, rlObj, kCoreReg);
- int regPtr = allocTemp(cUnit);
+ int regPtr = dvmCompilerAllocTemp(cUnit);
assert(rlDest.wide);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#endif
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
storeValueWide(cUnit, rlDest, rlResult);
}
static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 2);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 2);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
int regPtr;
rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
}
/*
int regPtr;
RegLocation rlResult;
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset,
NULL);/* null object? */
#if defined(WITH_SELF_VERIFICATION)
int fieldOffset)
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 1);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
int regPtr;
rlArray.lowReg, mir->offset, NULL);
}
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
- int regLen = allocTemp(cUnit);
+ int regLen = dvmCompilerAllocTemp(cUnit);
/* Get len */
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
/* regPtr -> array data */
opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
pcrLabel);
- freeTemp(cUnit, regLen);
+ dvmCompilerFreeTemp(cUnit, regLen);
} else {
/* regPtr -> array data */
opRegRegImm(cUnit, kOpAdd, regPtr, rlArray.lowReg, dataOffset);
}
if ((size == kLong) || (size == kDouble)) {
if (scale) {
- int rNewIndex = allocTemp(cUnit);
+ int rNewIndex = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
} else {
opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
}
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#endif
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
storeValueWide(cUnit, rlDest, rlResult);
} else {
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
#endif
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
storeValue(cUnit, rlDest, rlResult);
}
}
rlArray = loadValue(cUnit, rlArray, kCoreReg);
rlIndex = loadValue(cUnit, rlIndex, kCoreReg);
- if (isTemp(cUnit, rlArray.lowReg)) {
- clobberReg(cUnit, rlArray.lowReg);
+ if (dvmCompilerIsTemp(cUnit, rlArray.lowReg)) {
+ dvmCompilerClobber(cUnit, rlArray.lowReg);
regPtr = rlArray.lowReg;
} else {
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
genRegCopy(cUnit, regPtr, rlArray.lowReg);
}
}
if (!(mir->OptimizationFlags & MIR_IGNORE_RANGE_CHECK)) {
- int regLen = allocTemp(cUnit);
+ int regLen = dvmCompilerAllocTemp(cUnit);
//NOTE: max live temps(4) here.
/* Get len */
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLen);
opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
genBoundsCheck(cUnit, rlIndex.lowReg, regLen, mir->offset,
pcrLabel);
- freeTemp(cUnit, regLen);
+ dvmCompilerFreeTemp(cUnit, regLen);
} else {
/* regPtr -> array data */
opRegImm(cUnit, kOpAdd, regPtr, dataOffset);
if ((size == kLong) || (size == kDouble)) {
//TODO: need specific wide routine that can handle fp regs
if (scale) {
- int rNewIndex = allocTemp(cUnit);
+ int rNewIndex = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpLsl, rNewIndex, rlIndex.lowReg, scale);
opRegReg(cUnit, kOpAdd, regPtr, rNewIndex);
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
} else {
opRegReg(cUnit, kOpAdd, regPtr, rlIndex.lowReg);
}
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = false;
#endif
- freeTemp(cUnit, regPtr);
+ dvmCompilerFreeTemp(cUnit, regPtr);
} else {
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
#if defined(WITH_SELF_VERIFICATION)
default:
return true;
}
- rlResult = getReturnLocWide(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
return false;
}
switch (mir->dalvikInsn.opCode) {
case OP_NOT_LONG:
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOpMvn, rlResult.lowReg, rlSrc2.lowReg);
opRegReg(cUnit, kOpMvn, rlResult.highReg, rlSrc2.highReg);
storeValueWide(cUnit, rlDest, rlResult);
break;
case OP_NEG_LONG: {
//TUNING: can improve this using Thumb2 code
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, tReg, 0);
opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
tReg, rlSrc2.lowReg);
genLong3Addr(cUnit, firstOp, secondOp, rlDest, rlSrc1, rlSrc2);
} else {
// Adjust return regs in to handle case of rem returning r2/r3
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadConstant(cUnit, rlr, (int) callTgt);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
opReg(cUnit, kOpBlx, rlr);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (retReg == r0)
- rlResult = getReturnLocWide(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
else
- rlResult = getReturnLocWideAlt(cUnit);
+ rlResult = dvmCompilerGetReturnWideAlt(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
}
return false;
if (!callOut) {
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
if (unary) {
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, op, rlResult.lowReg,
rlSrc1.lowReg);
} else {
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
if (shiftOp) {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAnd, tReg, rlSrc2.lowReg, 31);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, op, rlResult.lowReg,
rlSrc1.lowReg, tReg);
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
} else {
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, op, rlResult.lowReg,
rlSrc1.lowReg, rlSrc2.lowReg);
}
storeValue(cUnit, rlDest, rlResult);
} else {
RegLocation rlResult;
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
loadValueDirectFixed(cUnit, rlSrc2, r1);
loadConstant(cUnit, r2, (int) callTgt);
loadValueDirectFixed(cUnit, rlSrc1, r0);
genNullCheck(cUnit, rlSrc2.sRegLow, r1, mir->offset, NULL);
}
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (retReg == r0)
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
else
- rlResult = getReturnLocAlt(cUnit);
+ rlResult = dvmCompilerGetReturnAlt(cUnit);
storeValue(cUnit, rlDest, rlResult);
}
return false;
RegLocation rlSrc2;
/* Deduce sizes of operands */
if (mir->ssaRep->numUses == 2) {
- rlSrc1 = getSrcLoc(cUnit, mir, 0);
- rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
} else if (mir->ssaRep->numUses == 3) {
- rlSrc1 = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc2 = getSrcLoc(cUnit, mir, 2);
+ rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
} else {
- rlSrc1 = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc2 = getSrcLocWide(cUnit, mir, 2, 3);
+ rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
assert(mir->ssaRep->numUses == 4);
}
if (mir->ssaRep->numDefs == 1) {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
} else {
assert(mir->ssaRep->numDefs == 2);
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
}
if ((opCode >= OP_ADD_LONG_2ADDR) && (opCode <= OP_XOR_LONG_2ADDR)) {
* live values, so we clobber them immediately after loading to prevent
* them from being used as sources for subsequent loads.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
for (i = 0; i < dInsn->vA; i++) {
regMask |= 1 << i;
- rlArg = getSrcLoc(cUnit, mir, numDone++);
+ rlArg = dvmCompilerGetSrc(cUnit, mir, numDone++);
loadValueDirectFixed(cUnit, rlArg, i);
}
if (regMask) {
sizeof(StackSaveArea) + (dInsn->vA << 2));
/* generate null check */
if (pcrLabel) {
- *pcrLabel = genNullCheck(cUnit, getSrcSSAName(mir, 0), r0,
+ *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
mir->offset, NULL);
}
storeMultiple(cUnit, r7, regMask);
* region - even though some might conceivably have valid copies
* cached in a preserved register.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
/*
* r4PC : &rFP[vC]
sizeof(StackSaveArea) + (numArgs << 2));
/* generate null check */
if (pcrLabel) {
- *pcrLabel = genNullCheck(cUnit, getSrcSSAName(mir, 0), r0,
+ *pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), r0,
mir->offset, NULL);
}
* memory by the point, so register usage restrictions no
* longer apply. All temp & preserved registers may be used.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
/* r1 = &retChainingCell */
- lockTemp(cUnit, r1);
+ dvmCompilerLockTemp(cUnit, r1);
ArmLIR *addrRetChain = opRegRegImm(cUnit, kOpAdd, r1, rpc, 0);
/* r4PC = dalvikCallsite */
loadConstant(cUnit, r4PC,
* longer apply. Lock temps to prevent them from being
* allocated by utility routines.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
/* "this" is already left in r0 by genProcessArgs* */
* memory by the point, so register usage restrictions no
* longer apply. All temp & preserved registers may be used.
*/
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
/* r3 now contains this->clazz */
loadWordDisp(cUnit, r0, offsetof(Object, clazz), r3);
static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
{
/* r0 = dalvik pc */
- flushAllRegs(cUnit);
+ dvmCompilerFlushAllRegs(cUnit);
loadConstant(cUnit, r0, (int) (cUnit->method->insns + offset));
loadWordDisp(cUnit, r0, offsetof(Object, clazz), r3);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState,
kInstrCanThrow;
//Ugly, but necessary. Flush all Dalvik regs so Interp can find them
- flushAllRegs(cUnit);
+ dvmCompilerFlushAllRegs(cUnit);
if ((mir->next == NULL) || (flags & flagsToCheck)) {
genPuntToInterp(cUnit, mir->offset);
{
bool isEnter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER);
genExportPC(cUnit, mir);
- flushAllRegs(cUnit); /* Send everything to home location */
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
loadValueDirectFixed(cUnit, rlSrc, r1);
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, self), r0);
genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
loadConstant(cUnit, r2, (int)dvmUnlockObject);
/* Do the call */
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
}
}
RegLocation rlDest;
RegLocation rlResult;
if (mir->ssaRep->numDefs == 2) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
switch (mir->dalvikInsn.opCode) {
case OP_CONST:
case OP_CONST_4: {
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstantValue(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
storeValue(cUnit, rlDest, rlResult);
break;
case OP_CONST_WIDE_32: {
//TUNING: single routine to load constant pair for support doubles
//TUNING: load 0/-1 separately to avoid load dependency
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, mir->dalvikInsn.vB);
opRegRegImm(cUnit, kOpAsr, rlResult.highReg,
rlResult.lowReg, 31);
RegLocation rlDest;
RegLocation rlResult;
if (mir->ssaRep->numDefs == 2) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
switch (mir->dalvikInsn.opCode) {
case OP_CONST_HIGH16: {
void *strPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResStrings[mir->dalvikInsn.vB]);
assert(strPtr != NULL);
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, (int) strPtr );
storeValue(cUnit, rlDest, rlResult);
break;
void *classPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vB]);
assert(classPtr != NULL);
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, (int) classPtr );
storeValue(cUnit, rlDest, rlResult);
break;
case OP_SGET_SHORT:
case OP_SGET: {
int valOffset = offsetof(StaticField, value);
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
assert(fieldPtr != NULL);
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
int valOffset = offsetof(StaticField, value);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
assert(fieldPtr != NULL);
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
cUnit->heapMemOp = true;
case OP_SPUT_SHORT:
case OP_SPUT: {
int valOffset = offsetof(StaticField, value);
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
assert(fieldPtr != NULL);
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
break;
}
case OP_SPUT_WIDE: {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
int valOffset = offsetof(StaticField, value);
void *fieldPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
assert(fieldPtr != NULL);
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
rlSrc = loadValueWide(cUnit, rlSrc, kAnyReg);
loadConstant(cUnit, tReg, (int) fieldPtr + valOffset);
#if defined(WITH_SELF_VERIFICATION)
* with. However, Alloc might throw, so we need to genExportPC()
*/
assert((classPtr->accessFlags & (ACC_INTERFACE|ACC_ABSTRACT)) == 0);
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
genExportPC(cUnit, mir);
loadConstant(cUnit, r2, (int)dvmAllocObject);
loadConstant(cUnit, r0, (int) classPtr);
loadConstant(cUnit, r1, ALLOC_DONT_TRACK);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* generate a branch over if allocation is successful */
opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
branchOver->generic.target = (LIR *) target;
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = getReturnLoc(cUnit);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
break;
}
genInterpSingleStep(cUnit, mir);
return false;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadConstant(cUnit, r1, (int) classPtr );
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0); /* Null? */
ArmLIR *branch1 = opCondBranch(cUnit, kArmCondEq);
opRegReg(cUnit, kOpCmp, r0, r1);
ArmLIR *branch2 = opCondBranch(cUnit, kArmCondEq);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/*
* If null, check cast failed - punt to the interpreter. Because
* interpreter will be the one throwing, we don't need to
case OP_MOVE_EXCEPTION: {
int offset = offsetof(InterpState, self);
int exOffset = offsetof(Thread, exception);
- int selfReg = allocTemp(cUnit);
- int resetReg = allocTemp(cUnit);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ int selfReg = dvmCompilerAllocTemp(cUnit);
+ int resetReg = dvmCompilerAllocTemp(cUnit);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadWordDisp(cUnit, rGLUE, offset, selfReg);
loadConstant(cUnit, resetReg, 0);
loadWordDisp(cUnit, selfReg, exOffset, rlResult.lowReg);
}
case OP_MOVE_RESULT:
case OP_MOVE_RESULT_OBJECT: {
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlSrc = LOC_DALVIK_RETURN_VAL;
rlSrc.fp = rlDest.fp;
storeValue(cUnit, rlDest, rlSrc);
break;
}
case OP_MOVE_RESULT_WIDE: {
- RegLocation rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
RegLocation rlSrc = LOC_DALVIK_RETURN_VAL_WIDE;
rlSrc.fp = rlDest.fp;
storeValueWide(cUnit, rlDest, rlSrc);
break;
}
case OP_RETURN_WIDE: {
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = LOC_DALVIK_RETURN_VAL_WIDE;
rlDest.fp = rlSrc.fp;
storeValueWide(cUnit, rlDest, rlSrc);
}
case OP_RETURN:
case OP_RETURN_OBJECT: {
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = LOC_DALVIK_RETURN_VAL;
rlDest.fp = rlSrc.fp;
storeValue(cUnit, rlDest, rlSrc);
}
if (mir->ssaRep->numUses == 2)
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
else
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
if (mir->ssaRep->numDefs == 2)
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
else
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
switch (opCode) {
case OP_DOUBLE_TO_INT:
storeValueWide(cUnit, rlDest, rlSrc);
break;
case OP_INT_TO_LONG:
- rlSrc = updateLoc(cUnit, rlSrc);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
//TUNING: shouldn't loadValueDirect already check for phys reg?
if (rlSrc.location == kLocPhysReg) {
genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
storeValueWide(cUnit, rlDest, rlResult);
break;
case OP_LONG_TO_INT:
- rlSrc = updateLocWide(cUnit, rlSrc);
- rlSrc = wideToNarrowLoc(cUnit, rlSrc);
+ rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
+ rlSrc = dvmCompilerWideToNarrow(cUnit, rlSrc);
// Intentional fallthrough
case OP_MOVE:
case OP_MOVE_OBJECT:
break;
case OP_INT_TO_BYTE:
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOp2Byte, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
break;
case OP_INT_TO_SHORT:
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOp2Short, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
break;
case OP_INT_TO_CHAR:
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOp2Char, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
break;
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
genNullCheck(cUnit, rlSrc.sRegLow, rlSrc.lowReg,
mir->offset, NULL);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadWordDisp(cUnit, rlSrc.lowReg, lenOffset,
rlResult.lowReg);
storeValue(cUnit, rlDest, rlResult);
RegLocation rlResult;
int BBBB = mir->dalvikInsn.vB;
if (dalvikOpCode == OP_CONST_WIDE_16) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg, BBBB);
//TUNING: do high separately to avoid load dependency
opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31);
storeValueWide(cUnit, rlDest, rlResult);
} else if (dalvikOpCode == OP_CONST_16) {
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kAnyReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true);
loadConstantValue(cUnit, rlResult.lowReg, BBBB);
storeValue(cUnit, rlDest, rlResult);
} else
{
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
ArmConditionCode cond;
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0);
static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
{
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
int lit = mir->dalvikInsn.vC;
OpKind op = 0; /* Make gcc happy */
int tReg;
//TUNING: add support for use of Arm rsub op
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- tReg = allocTemp(cUnit);
+ tReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, tReg, lit);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, kOpSub, rlResult.lowReg,
tReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
genInterpSingleStep(cUnit, mir);
return false;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
if ((dalvikOpCode == OP_DIV_INT_LIT8) ||
(dalvikOpCode == OP_DIV_INT_LIT16)) {
loadConstant(cUnit, r2, (int)__aeabi_idiv);
}
loadConstant(cUnit, r1, lit);
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
if (isDiv)
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
else
- rlResult = getReturnLocAlt(cUnit);
+ rlResult = dvmCompilerGetReturnAlt(cUnit);
storeValue(cUnit, rlDest, rlResult);
return false;
break;
return true;
}
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
// Avoid shifts by literal 0 - no support in Thumb. Change to copy
if (shiftOp && (lit == 0)) {
genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
switch (dalvikOpCode) {
case OP_NEW_ARRAY: {
// Generates a call - use explicit registers
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
void *classPtr = (void*)
(cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
assert(classPtr != NULL);
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
genExportPC(cUnit, mir);
loadValueDirectFixed(cUnit, rlSrc, r1); /* Len */
loadConstant(cUnit, r0, (int) classPtr );
genRegImmCheck(cUnit, kArmCondMi, r1, 0, mir->offset, NULL);
loadConstant(cUnit, r2, ALLOC_DONT_TRACK);
opReg(cUnit, kOpBlx, r3);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* generate a branch over if allocation is successful */
opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
branchOver->generic.target = (LIR *) target;
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
break;
}
case OP_INSTANCE_OF: {
// May generate a call - use explicit registers
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- RegLocation rlDest = getDestLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0);
RegLocation rlResult;
ClassObject *classPtr =
(cUnit->method->clazz->pDvmDex->pResClasses[mir->dalvikInsn.vC]);
genInterpSingleStep(cUnit, mir);
break;
}
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0); /* Ref */
loadConstant(cUnit, r2, (int) classPtr );
//TUNING: compare to 0 primative to allow use of CB[N]Z
genRegCopy(cUnit, r0, r1);
genRegCopy(cUnit, r1, r2);
opReg(cUnit, kOpBlx, r3);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* branch target here */
ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
target->defMask = ENCODE_ALL;
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
branch1->generic.target = (LIR *)target;
branch2->generic.target = (LIR *)target;
{
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
ArmConditionCode cond;
- RegLocation rlSrc1 = getSrcLoc(cUnit, mir, 0);
- RegLocation rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
case OP_MOVE_OBJECT_16:
case OP_MOVE_FROM16:
case OP_MOVE_OBJECT_FROM16: {
- storeValue(cUnit, getDestLoc(cUnit, mir, 0),
- getSrcLoc(cUnit, mir, 0));
+ storeValue(cUnit, dvmCompilerGetDest(cUnit, mir, 0),
+ dvmCompilerGetSrc(cUnit, mir, 0));
break;
}
case OP_MOVE_WIDE_16:
case OP_MOVE_WIDE_FROM16: {
- storeValueWide(cUnit, getDestLocWide(cUnit, mir, 0, 1),
- getSrcLocWide(cUnit, mir, 0, 1));
+ storeValueWide(cUnit, dvmCompilerGetDestWide(cUnit, mir, 0, 1),
+ dvmCompilerGetSrcWide(cUnit, mir, 0, 1));
break;
}
default:
/* APUTs have 3 sources and no targets */
if (mir->ssaRep->numDefs == 0) {
if (mir->ssaRep->numUses == 3) {
- rlDest = getSrcLoc(cUnit, mir, 0);
- rlSrc1 = getSrcLoc(cUnit, mir, 1);
- rlSrc2 = getSrcLoc(cUnit, mir, 2);
+ rlDest = dvmCompilerGetSrc(cUnit, mir, 0);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 1);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 2);
} else {
assert(mir->ssaRep->numUses == 4);
- rlDest = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc1 = getSrcLoc(cUnit, mir, 2);
- rlSrc2 = getSrcLoc(cUnit, mir, 3);
+ rlDest = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 2);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 3);
}
} else {
/* Two sources and 1 dest. Deduce the operand sizes */
if (mir->ssaRep->numUses == 4) {
- rlSrc1 = getSrcLocWide(cUnit, mir, 0, 1);
- rlSrc2 = getSrcLocWide(cUnit, mir, 2, 3);
+ rlSrc1 = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
+ rlSrc2 = dvmCompilerGetSrcWide(cUnit, mir, 2, 3);
} else {
assert(mir->ssaRep->numUses == 2);
- rlSrc1 = getSrcLoc(cUnit, mir, 0);
- rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
}
if (mir->ssaRep->numDefs == 2) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
assert(mir->ssaRep->numDefs == 1);
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
}
OpCode dalvikOpCode = mir->dalvikInsn.opCode;
switch (dalvikOpCode) {
case OP_FILL_ARRAY_DATA: {
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
// Making a call - use explicit registers
- flushAllRegs(cUnit); /* Send everything to home location */
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
genExportPC(cUnit, mir);
loadValueDirectFixed(cUnit, rlSrc, r0);
loadConstant(cUnit, r2, (int)dvmInterpHandleFillArrayData);
loadConstant(cUnit, r1,
(int) (cUnit->method->insns + mir->offset + mir->dalvikInsn.vB));
opReg(cUnit, kOpBlx, r2);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* generate a branch over if successful */
opRegImm(cUnit, kOpCmp, r0, 0); /* NULL? */
ArmLIR *branchOver = opCondBranch(cUnit, kArmCondNe);
*/
case OP_PACKED_SWITCH:
case OP_SPARSE_SWITCH: {
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
- flushAllRegs(cUnit); /* Send everything to home location */
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r1);
- lockAllTemps(cUnit);
+ dvmCompilerLockAllTemps(cUnit);
const u2 *switchData =
cUnit->method->insns + mir->offset + mir->dalvikInsn.vB;
u2 size = switchData[1];
/* r2 <- pc of the instruction following the blx */
opRegReg(cUnit, kOpMov, r2, rpc);
opReg(cUnit, kOpBlx, r4PC);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
/* pc <- computed goto target */
opRegReg(cUnit, kOpMov, rpc, r0);
break;
int methodIndex = dInsn->vB;
/* Ensure that nothing is both live and dirty */
- flushAllRegs(cUnit);
+ dvmCompilerFlushAllRegs(cUnit);
if (mir->dalvikInsn.opCode == OP_INVOKE_INTERFACE)
genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel);
return false;
#else
ArmLIR *rollback;
- RegLocation rlThis = getSrcLoc(cUnit, mir, 0);
- RegLocation rlComp = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlComp = dvmCompilerGetSrc(cUnit, mir, 1);
loadValueDirectFixed(cUnit, rlThis, r0);
loadValueDirectFixed(cUnit, rlComp, r1);
* expansion.
*/
genDispatchToHandler(cUnit, TEMPLATE_STRING_COMPARETO);
- storeValue(cUnit, inlinedTarget(cUnit, mir, false), getReturnLoc(cUnit));
+ storeValue(cUnit, inlinedTarget(cUnit, mir, false),
+ dvmCompilerGetReturn(cUnit));
return true;
#endif
}
#if defined(USE_GLOBAL_STRING_DEFS)
return false;
#else
- RegLocation rlThis = getSrcLoc(cUnit, mir, 0);
- RegLocation rlChar = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlThis = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlChar = dvmCompilerGetSrc(cUnit, mir, 1);
loadValueDirectFixed(cUnit, rlThis, r0);
loadValueDirectFixed(cUnit, rlChar, r1);
if (!singleI) {
- RegLocation rlStart = getSrcLoc(cUnit, mir, 2);
+ RegLocation rlStart = dvmCompilerGetSrc(cUnit, mir, 2);
loadValueDirectFixed(cUnit, rlStart, r2);
} else {
loadConstant(cUnit, r2, 0);
/* Test objects for NULL */
genNullCheck(cUnit, rlThis.sRegLow, r0, mir->offset, NULL);
genDispatchToHandler(cUnit, TEMPLATE_STRING_INDEXOF);
- storeValue(cUnit, inlinedTarget(cUnit, mir, false), getReturnLoc(cUnit));
+ storeValue(cUnit, inlinedTarget(cUnit, mir, false),
+ dvmCompilerGetReturn(cUnit));
return true;
#endif
}
default:
dvmAbort();
}
- flushAllRegs(cUnit); /* Send everything to home location */
- clobberCallRegs(cUnit);
- clobberReg(cUnit, r4PC);
- clobberReg(cUnit, r7);
+ dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */
+ dvmCompilerColbberCallRegs(cUnit);
+ dvmCompilerClobber(cUnit, r4PC);
+ dvmCompilerClobber(cUnit, r7);
opRegRegImm(cUnit, kOpAdd, r4PC, rGLUE, offset);
opImm(cUnit, kOpPush, (1<<r4PC) | (1<<r7));
loadConstant(cUnit, r4PC, (int)inLineTable[operation].func);
genExportPC(cUnit, mir);
for (i=0; i < dInsn->vA; i++) {
- loadValueDirect(cUnit, getSrcLoc(cUnit, mir, i), i);
+ loadValueDirect(cUnit, dvmCompilerGetSrc(cUnit, mir, i), i);
}
opReg(cUnit, kOpBlx, r4PC);
opRegImm(cUnit, kOpAdd, r13, 8);
static bool handleFmt51l(CompilationUnit *cUnit, MIR *mir)
{
//TUNING: We're using core regs here - not optimal when target is a double
- RegLocation rlDest = getDestLocWide(cUnit, mir, 0, 1);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ RegLocation rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstantValue(cUnit, rlResult.lowReg,
mir->dalvikInsn.vB_wide & 0xFFFFFFFFUL);
loadConstantValue(cUnit, rlResult.highReg,
(ArmLIR *) cUnit->loopAnalysis->branchToPCR);
/* regLength <- len(arrayRef) */
- regLength = allocTemp(cUnit);
+ regLength = dvmCompilerAllocTemp(cUnit);
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
int delta = maxC;
}
if (delta) {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, tReg, rlIdxEnd.lowReg, delta);
rlIdxEnd.lowReg = tReg;
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
}
/* Punt if "regIdxEnd < len(Array)" is false */
genRegRegCheck(cUnit, kArmCondGe, rlIdxEnd.lowReg, regLength, 0,
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
const int lenOffset = offsetof(ArrayObject, length);
- const int regLength = allocTemp(cUnit);
+ const int regLength = dvmCompilerAllocTemp(cUnit);
const int maxC = dInsn->arg[0];
const int minC = dInsn->arg[1];
RegLocation rlArray = cUnit->regLocation[mir->dalvikInsn.vA];
loadWordDisp(cUnit, rlArray.lowReg, lenOffset, regLength);
if (maxC) {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, tReg, rlIdxInit.lowReg, maxC);
rlIdxInit.lowReg = tReg;
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
}
/* Punt if "regIdxInit < len(Array)" is false */
} else if (blockList[i]->blockType == kDalvikByteCode) {
labelList[i].opCode = kArmPseudoNormalBlockLabel;
/* Reset the register state */
- resetRegPool(cUnit);
- clobberAllRegs(cUnit);
- resetNullCheckTracker(cUnit);
+ dvmCompilerResetRegPool(cUnit);
+ dvmCompilerClobberAllRegs(cUnit);
+ dvmCompilerResetNullCheck(cUnit);
} else {
switch (blockList[i]->blockType) {
case kChainingCellNormal:
for (mir = blockList[i]->firstMIRInsn; mir; mir = mir->next) {
- resetRegPool(cUnit);
+ dvmCompilerResetRegPool(cUnit);
if (gDvmJit.disableOpt & (1 << kTrackLiveTemps)) {
- clobberAllRegs(cUnit);
+ dvmCompilerClobberAllRegs(cUnit);
}
if (gDvmJit.disableOpt & (1 << kSuppressLoads)) {
- resetDefTracking(cUnit);
+ dvmCompilerResetDefTracking(cUnit);
}
if (mir->dalvikInsn.opCode >= kMirOpFirst) {
static void loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc,
int reg1)
{
- rlSrc = updateLoc(cUnit, rlSrc); /* Is our value hiding in a live temp? */
+ rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
genRegCopy(cUnit, reg1, rlSrc.lowReg);
} else if (rlSrc.location == kLocRetval) {
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, retval), reg1);
} else {
assert(rlSrc.location == kLocDalvikFrame);
- loadWordDisp(cUnit, rFP, sReg2vReg(cUnit, rlSrc.sRegLow) << 2,
+ loadWordDisp(cUnit, rFP, dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2,
reg1);
}
}
static void loadValueDirectFixed(CompilationUnit *cUnit, RegLocation rlSrc,
int reg1)
{
- clobberReg(cUnit, reg1);
- markRegInUse(cUnit, reg1);
+ dvmCompilerClobber(cUnit, reg1);
+ dvmcompilerMarkInUse(cUnit, reg1);
loadValueDirect(cUnit, rlSrc, reg1);
}
static void loadValueDirectWide(CompilationUnit *cUnit, RegLocation rlSrc,
int regLo, int regHi)
{
- rlSrc = updateLocWide(cUnit, rlSrc);
+ rlSrc = dvmCompilerUpdateLocWide(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
genRegCopyWide(cUnit, regLo, regHi, rlSrc.lowReg, rlSrc.highReg);
} else if (rlSrc.location == kLocRetval) {
} else {
assert(rlSrc.location == kLocDalvikFrame);
loadBaseDispWide(cUnit, NULL, rFP,
- sReg2vReg(cUnit, rlSrc.sRegLow) << 2,
+ dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2,
regLo, regHi, INVALID_SREG);
}
}
static void loadValueDirectWideFixed(CompilationUnit *cUnit, RegLocation rlSrc,
int regLo, int regHi)
{
- clobberReg(cUnit, regLo);
- clobberReg(cUnit, regHi);
- markRegInUse(cUnit, regLo);
- markRegInUse(cUnit, regHi);
+ dvmCompilerClobber(cUnit, regLo);
+ dvmCompilerClobber(cUnit, regHi);
+ dvmcompilerMarkInUse(cUnit, regLo);
+ dvmcompilerMarkInUse(cUnit, regHi);
loadValueDirectWide(cUnit, rlSrc, regLo, regHi);
}
RegisterClass opKind)
{
RegisterInfo *pReg;
- rlSrc = evalLoc(cUnit, rlSrc, opKind, false);
+ rlSrc = dvmCompilerEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
loadValueDirect(cUnit, rlSrc, rlSrc.lowReg);
rlSrc.location = kLocPhysReg;
- markRegLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
+ dvmCompilerMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
} else if (rlSrc.location == kLocRetval) {
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, retval), rlSrc.lowReg);
rlSrc.location = kLocPhysReg;
- clobberReg(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
}
return rlSrc;
}
LIR *defEnd;
assert(!rlDest.wide);
assert(!rlSrc.wide);
- killNullCheckedLocation(cUnit, rlDest);
- rlSrc = updateLoc(cUnit, rlSrc);
- rlDest = updateLoc(cUnit, rlDest);
+ dvmCompilerKillNullCheckedLoc(cUnit, rlDest);
+ rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
+ rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
if (rlSrc.location == kLocPhysReg) {
- if (isLive(cUnit, rlSrc.lowReg) || (rlDest.location == kLocPhysReg)) {
+ if (dvmCompilerIsLive(cUnit, rlSrc.lowReg) ||
+ (rlDest.location == kLocPhysReg)) {
// Src is live or Dest has assigned reg.
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
genRegCopy(cUnit, rlDest.lowReg, rlSrc.lowReg);
} else {
// Just re-assign the registers. Dest gets Src's regs
rlDest.lowReg = rlSrc.lowReg;
- clobberReg(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
}
} else {
// Load Src either into promoted Dest or temps allocated for Dest
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
loadValueDirect(cUnit, rlSrc, rlDest.lowReg);
}
// Dest is now live and dirty (until/if we flush it to home location)
- markRegLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
- markRegDirty(cUnit, rlDest.lowReg);
+ dvmCompilerMarkLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
+ dvmCompilerMarkDirty(cUnit, rlDest.lowReg);
if (rlDest.location == kLocRetval) {
storeBaseDisp(cUnit, rGLUE, offsetof(InterpState, retval),
rlDest.lowReg, kWord);
- clobberReg(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
} else {
- resetDefLoc(cUnit, rlDest);
- if (liveOut(cUnit, rlDest.sRegLow)) {
+ dvmCompilerResetDefLoc(cUnit, rlDest);
+ if (dvmCompilerLiveOut(cUnit, rlDest.sRegLow)) {
defStart = (LIR *)cUnit->lastLIRInsn;
- int vReg = sReg2vReg(cUnit, rlDest.sRegLow);
+ int vReg = dvmCompilerS2VReg(cUnit, rlDest.sRegLow);
storeBaseDisp(cUnit, rFP, vReg << 2, rlDest.lowReg, kWord);
- markRegClean(cUnit, rlDest.lowReg);
+ dvmCompilerMarkClean(cUnit, rlDest.lowReg);
defEnd = (LIR *)cUnit->lastLIRInsn;
- markDef(cUnit, rlDest, defStart, defEnd);
+ dvmCompilerMarkDef(cUnit, rlDest, defStart, defEnd);
}
}
}
RegisterInfo *pRegLo;
RegisterInfo *pRegHi;
assert(rlSrc.wide);
- rlSrc = evalLoc(cUnit, rlSrc, opKind, false);
+ rlSrc = dvmCompilerEvalLoc(cUnit, rlSrc, opKind, false);
if (rlSrc.location == kLocDalvikFrame) {
loadValueDirectWide(cUnit, rlSrc, rlSrc.lowReg, rlSrc.highReg);
rlSrc.location = kLocPhysReg;
- markRegLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
- markRegLive(cUnit, rlSrc.highReg, hiSReg(rlSrc.sRegLow));
+ dvmCompilerMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow);
+ dvmCompilerMarkLive(cUnit, rlSrc.highReg,
+ dvmCompilerSRegHi(rlSrc.sRegLow));
} else if (rlSrc.location == kLocRetval) {
loadBaseDispWide(cUnit, NULL, rGLUE, offsetof(InterpState, retval),
rlSrc.lowReg, rlSrc.highReg, INVALID_SREG);
rlSrc.location = kLocPhysReg;
- clobberReg(cUnit, rlSrc.lowReg);
- clobberReg(cUnit, rlSrc.highReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.highReg);
}
return rlSrc;
}
assert(FPREG(rlSrc.lowReg)==FPREG(rlSrc.highReg));
assert(rlDest.wide);
assert(rlSrc.wide);
- killNullCheckedLocation(cUnit, rlDest);
+ dvmCompilerKillNullCheckedLoc(cUnit, rlDest);
if (rlSrc.location == kLocPhysReg) {
- if (isLive(cUnit, rlSrc.lowReg) || isLive(cUnit, rlSrc.highReg) ||
+ if (dvmCompilerIsLive(cUnit, rlSrc.lowReg) ||
+ dvmCompilerIsLive(cUnit, rlSrc.highReg) ||
(rlDest.location == kLocPhysReg)) {
// Src is live or Dest has assigned reg.
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
genRegCopyWide(cUnit, rlDest.lowReg, rlDest.highReg,
rlSrc.lowReg, rlSrc.highReg);
} else {
// Just re-assign the registers. Dest gets Src's regs
rlDest.lowReg = rlSrc.lowReg;
rlDest.highReg = rlSrc.highReg;
- clobberReg(cUnit, rlSrc.lowReg);
- clobberReg(cUnit, rlSrc.highReg);
+ dvmCompilerClobber(cUnit, rlSrc.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc.highReg);
}
} else {
// Load Src either into promoted Dest or temps allocated for Dest
- rlDest = evalLoc(cUnit, rlDest, kAnyReg, false);
+ rlDest = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, false);
loadValueDirectWide(cUnit, rlSrc, rlDest.lowReg,
rlDest.highReg);
}
// Dest is now live and dirty (until/if we flush it to home location)
- markRegLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
- markRegLive(cUnit, rlDest.highReg, hiSReg(rlDest.sRegLow));
- markRegDirty(cUnit, rlDest.lowReg);
- markRegDirty(cUnit, rlDest.highReg);
- markRegPair(cUnit, rlDest.lowReg, rlDest.highReg);
+ dvmCompilerMarkLive(cUnit, rlDest.lowReg, rlDest.sRegLow);
+ dvmCompilerMarkLive(cUnit, rlDest.highReg,
+ dvmCompilerSRegHi(rlDest.sRegLow));
+ dvmCompilerMarkDirty(cUnit, rlDest.lowReg);
+ dvmCompilerMarkDirty(cUnit, rlDest.highReg);
+ dvmCompilerMarkPair(cUnit, rlDest.lowReg, rlDest.highReg);
if (rlDest.location == kLocRetval) {
storeBaseDispWide(cUnit, rGLUE, offsetof(InterpState, retval),
rlDest.lowReg, rlDest.highReg);
- clobberReg(cUnit, rlDest.lowReg);
- clobberReg(cUnit, rlDest.highReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.highReg);
} else {
- resetDefLocWide(cUnit, rlDest);
- if (liveOut(cUnit, rlDest.sRegLow) ||
- liveOut(cUnit, hiSReg(rlDest.sRegLow))) {
+ dvmCompilerResetDefLocWide(cUnit, rlDest);
+ if (dvmCompilerLiveOut(cUnit, rlDest.sRegLow) ||
+ dvmCompilerLiveOut(cUnit, dvmCompilerSRegHi(rlDest.sRegLow))) {
defStart = (LIR *)cUnit->lastLIRInsn;
- int vReg = sReg2vReg(cUnit, rlDest.sRegLow);
- assert((vReg+1) == sReg2vReg(cUnit, hiSReg(rlDest.sRegLow)));
+ int vReg = dvmCompilerS2VReg(cUnit, rlDest.sRegLow);
+ assert((vReg+1) == dvmCompilerS2VReg(cUnit,
+ dvmCompilerSRegHi(rlDest.sRegLow)));
storeBaseDispWide(cUnit, rFP, vReg << 2, rlDest.lowReg,
rlDest.highReg);
- markRegClean(cUnit, rlDest.lowReg);
- markRegClean(cUnit, rlDest.highReg);
+ dvmCompilerMarkClean(cUnit, rlDest.lowReg);
+ dvmCompilerMarkClean(cUnit, rlDest.highReg);
defEnd = (LIR *)cUnit->lastLIRInsn;
- markDefWide(cUnit, rlDest, defStart, defEnd);
+ dvmCompilerMarkDefWide(cUnit, rlDest, defStart, defEnd);
}
}
}
* we fake BLX_1 is a two operand instruction and the absolute target
* address is stored in operand[1].
*/
- clobberHandlerRegs(cUnit);
+ dvmCompilerClobberHandlerRegs(cUnit);
newLIR2(cUnit, kThumbBlx1,
(int) gDvmJit.codeCache + templateEntryOffsets[opCode],
(int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
}
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR3(cUnit, op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
storeValue(cUnit, rlDest, rlResult);
return false;
assert(rlSrc1.wide);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
assert(rlSrc2.wide);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
assert(rlDest.wide);
assert(rlResult.wide);
newLIR3(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg),
return true;
}
if (longSrc) {
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
} else {
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
if (longDest) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg), srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, op, rlResult.lowReg, srcReg);
storeValue(cUnit, rlDest, rlResult);
}
{
ArmLIR *branch;
DecodedInstruction *dInsn = &mir->dalvikInsn;
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, true);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vsqrtd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc.lowReg, rlSrc.highReg));
newLIR2(cUnit, kThumb2Vcmpd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlResult.lowReg, rlResult.highReg));
newLIR0(cUnit, kThumb2Fmstat);
branch = newLIR2(cUnit, kThumbBCond, 0, kArmCondEq);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
loadConstant(cUnit, r2, (int)sqrt);
newLIR3(cUnit, kThumb2Fmrrd, r0, r1, S2D(rlSrc.lowReg, rlSrc.highReg));
newLIR1(cUnit, kThumbBlxR, r2);
if (isDouble) {
rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
- clobberSReg(cUnit, rlDest.sRegLow);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ dvmCompilerClobberSReg(cUnit, rlDest.sRegLow);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstant(cUnit, rlResult.lowReg, defaultResult);
newLIR2(cUnit, kThumb2Vcmpd, S2D(rlSrc1.lowReg, r1Src2.highReg),
S2D(rlSrc2.lowReg, rlSrc2.highReg));
} else {
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
- clobberSReg(cUnit, rlDest.sRegLow);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ dvmCompilerClobberSReg(cUnit, rlDest.sRegLow);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstant(cUnit, rlResult.lowReg, defaultResult);
newLIR2(cUnit, kThumb2Vcmps, rlSrc1.lowReg, rlSrc2.lowReg);
}
static void loadValueAddress(CompilationUnit *cUnit, RegLocation rlSrc,
int rDest)
{
- rlSrc = rlSrc.wide ? updateLocWide(cUnit, rlSrc) : updateLoc(cUnit, rlSrc);
+ rlSrc = rlSrc.wide ? dvmCompilerUpdateLocWide(cUnit, rlSrc) :
+ dvmCompilerUpdateLoc(cUnit, rlSrc);
if (rlSrc.location == kLocPhysReg) {
if (rlSrc.wide) {
dvmCompilerFlushRegWideForV5TEVFP(cUnit, rlSrc.lowReg,
}
}
opRegRegImm(cUnit, kOpAdd, rDest, rFP,
- sReg2vReg(cUnit, rlSrc.sRegLow) << 2);
+ dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2);
}
static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlResult = LOC_C_RETURN_WIDE;
RegLocation rlDest = LOC_DALVIK_RETURN_VAL_WIDE;
loadValueAddress(cUnit, rlSrc, r2);
return true;
}
loadValueAddress(cUnit, rlDest, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc1, r1);
- clobberReg(cUnit, r1);
+ dvmCompilerClobber(cUnit, r1);
loadValueAddress(cUnit, rlSrc2, r2);
genDispatchToHandler(cUnit, opCode);
- rlDest = updateLoc(cUnit, rlDest);
+ rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
if (rlDest.location == kLocPhysReg) {
- clobberReg(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
}
return false;
}
return true;
}
loadValueAddress(cUnit, rlDest, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc1, r1);
- clobberReg(cUnit, r1);
+ dvmCompilerClobber(cUnit, r1);
loadValueAddress(cUnit, rlSrc2, r2);
genDispatchToHandler(cUnit, opCode);
- rlDest = updateLocWide(cUnit, rlDest);
+ rlDest = dvmCompilerUpdateLocWide(cUnit, rlDest);
if (rlDest.location == kLocPhysReg) {
- clobberReg(cUnit, rlDest.lowReg);
- clobberReg(cUnit, rlDest.highReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.highReg);
}
return false;
}
}
if (longSrc) {
- rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
} else {
- rlSrc = getSrcLoc(cUnit, mir, 0);
+ rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
}
if (longDest) {
- rlDest = getDestLocWide(cUnit, mir, 0, 1);
+ rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
} else {
- rlDest = getDestLoc(cUnit, mir, 0);
+ rlDest = dvmCompilerGetDest(cUnit, mir, 0);
}
loadValueAddress(cUnit, rlDest, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc, r1);
genDispatchToHandler(cUnit, template);
if (rlDest.wide) {
- rlDest = updateLocWide(cUnit, rlDest);
- clobberReg(cUnit, rlDest.highReg);
+ rlDest = dvmCompilerUpdateLocWide(cUnit, rlDest);
+ dvmCompilerClobber(cUnit, rlDest.highReg);
} else {
- rlDest = updateLoc(cUnit, rlDest);
+ rlDest = dvmCompilerUpdateLoc(cUnit, rlDest);
}
- clobberReg(cUnit, rlDest.lowReg);
+ dvmCompilerClobber(cUnit, rlDest.lowReg);
return false;
}
static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2)
+ RegLocation rlSrc1, RegLocation rlSrc2)
{
TemplateOpCode template;
- RegLocation rlResult = getReturnLoc(cUnit);
+ RegLocation rlResult = dvmCompilerGetReturn(cUnit);
bool wide = true;
switch(mir->dalvikInsn.opCode) {
return true;
}
loadValueAddress(cUnit, rlSrc1, r0);
- clobberReg(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
loadValueAddress(cUnit, rlSrc2, r1);
genDispatchToHandler(cUnit, template);
storeValue(cUnit, rlDest, rlResult);
#include "compiler/Dataflow.h"
#include "compiler/codegen/arm/ArmLIR.h"
-/*
- * The following are register allocation routines exposed to the code generator
- * FIXME - dvmCompiler prefixes are not added yet
- */
-
-static inline int sReg2vReg(CompilationUnit *cUnit, int sReg)
+static inline int dvmCompilerS2VReg(CompilationUnit *cUnit, int sReg)
{
assert(sReg != INVALID_SREG);
return DECODE_REG(dvmConvertSSARegToDalvik(cUnit, sReg));
}
/* Reset the tracker to unknown state */
-static inline void resetNullCheckTracker(CompilationUnit *cUnit)
+static inline void dvmCompilerResetNullCheck(CompilationUnit *cUnit)
{
dvmClearAllBits(cUnit->regPool->nullCheckedRegs);
}
* identified by the dataflow pass what it's new name is.
*/
-static inline int hiSReg(int lowSreg) {
+static inline int dvmCompilerSRegHi(int lowSreg) {
return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1;
}
-static inline bool liveOut(CompilationUnit *cUnit, int sReg)
+static inline bool dvmCompilerLiveOut(CompilationUnit *cUnit, int sReg)
{
//TODO: fully implement
return true;
}
-static inline int getSrcSSAName(MIR *mir, int num)
+static inline int dvmCompilerSSASrc(MIR *mir, int num)
{
assert(mir->ssaRep->numUses > num);
return mir->ssaRep->uses[num];
}
-extern RegLocation evalLoc(CompilationUnit *cUnit, RegLocation loc,
- int regClass, bool update);
+extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
+ int regClass, bool update);
/* Mark a temp register as dead. Does not affect allocation state. */
-extern void clobberReg(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
-extern RegLocation updateLoc(CompilationUnit *cUnit, RegLocation loc);
+extern RegLocation dvmCompilerUpdateLoc(CompilationUnit *cUnit,
+ RegLocation loc);
/* see comments for updateLoc */
-extern RegLocation updateLocWide(CompilationUnit *cUnit, RegLocation loc);
+extern RegLocation dvmCompilerUpdateLocWide(CompilationUnit *cUnit,
+ RegLocation loc);
/* Clobber all of the temps that might be used by a handler. */
-extern void clobberHandlerRegs(CompilationUnit *cUnit);
+extern void dvmCompilerClobberHandlerRegs(CompilationUnit *cUnit);
-extern void markRegLive(CompilationUnit *cUnit, int reg, int sReg);
+extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg);
-extern void markRegDirty(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg);
-extern void markRegPair(CompilationUnit *cUnit, int lowReg, int highReg);
+extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg,
+ int highReg);
-extern void markRegClean(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg);
-extern void resetDef(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg);
-extern void resetDefLoc(CompilationUnit *cUnit, RegLocation rl);
+extern void dvmCompilerResetDefLoc(CompilationUnit *cUnit, RegLocation rl);
/* Set up temp & preserved register pools specialized by target */
-extern void initPool(RegisterInfo *regs, int *regNums, int num);
+extern void dvmCompilerInitPool(RegisterInfo *regs, int *regNums, int num);
/*
* Mark the beginning and end LIR of a def sequence. Note that
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDef(CompilationUnit *cUnit, RegLocation rl,
- LIR *start, LIR *finish);
+extern void dvmCompilerMarkDef(CompilationUnit *cUnit, RegLocation rl,
+ LIR *start, LIR *finish);
/*
* Mark the beginning and end LIR of a def sequence. Note that
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDefWide(CompilationUnit *cUnit, RegLocation rl,
- LIR *start, LIR *finish);
+extern void dvmCompilerMarkDefWide(CompilationUnit *cUnit, RegLocation rl,
+ LIR *start, LIR *finish);
-extern RegLocation getSrcLocWide(CompilationUnit *cUnit, MIR *mir,
+extern RegLocation dvmCompilerGetSrcWide(CompilationUnit *cUnit, MIR *mir,
int low, int high);
-extern RegLocation getDestLocWide(CompilationUnit *cUnit, MIR *mir,
- int low, int high);
+extern RegLocation dvmCompilerGetDestWide(CompilationUnit *cUnit, MIR *mir,
+ int low, int high);
// Get the LocRecord associated with an SSA name use.
-extern RegLocation getSrcLoc(CompilationUnit *cUnit, MIR *mir, int num);
+extern RegLocation dvmCompilerGetSrc(CompilationUnit *cUnit, MIR *mir, int num);
// Get the LocRecord associated with an SSA name def.
-extern RegLocation getDestLoc(CompilationUnit *cUnit, MIR *mir, int num);
+extern RegLocation dvmCompilerGetDest(CompilationUnit *cUnit, MIR *mir,
+ int num);
-extern RegLocation getReturnLocWide(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturnWide(CompilationUnit *cUnit);
/* Clobber all regs that might be used by an external C call */
-extern void clobberCallRegs(CompilationUnit *cUnit);
+extern void dvmCompilerColbberCallRegs(CompilationUnit *cUnit);
-extern RegisterInfo *isTemp(CompilationUnit *cUnit, int reg);
+extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg);
-extern void markRegInUse(CompilationUnit *cUnit, int reg);
+extern void dvmcompilerMarkInUse(CompilationUnit *cUnit, int reg);
-extern int allocTemp(CompilationUnit *cUnit);
+extern int dvmCompilerAllocTemp(CompilationUnit *cUnit);
-extern int allocTempFloat(CompilationUnit *cUnit);
+extern int dvmCompilerAllocTempFloat(CompilationUnit *cUnit);
//REDO: too many assumptions.
-extern int allocTempDouble(CompilationUnit *cUnit);
+extern int dvmCompilerAllocTempDouble(CompilationUnit *cUnit);
-extern void freeTemp(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg);
-extern void resetDefLocWide(CompilationUnit *cUnit, RegLocation rl);
+extern void dvmCompilerResetDefLocWide(CompilationUnit *cUnit, RegLocation rl);
-extern void resetDefTracking(CompilationUnit *cUnit);
+extern void dvmCompilerResetDefTracking(CompilationUnit *cUnit);
/* Kill the corresponding bit in the null-checked register list */
-extern void killNullCheckedLocation(CompilationUnit *cUnit, RegLocation loc);
+extern void dvmCompilerKillNullCheckedLoc(CompilationUnit *cUnit,
+ RegLocation loc);
//FIXME - this needs to also check the preserved pool.
-extern RegisterInfo *isLive(CompilationUnit *cUnit, int reg);
+extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg);
/* To be used when explicitly managing register use */
-extern void lockAllTemps(CompilationUnit *cUnit);
+extern void dvmCompilerLockAllTemps(CompilationUnit *cUnit);
-extern void flushAllRegs(CompilationUnit *cUnit);
+extern void dvmCompilerFlushAllRegs(CompilationUnit *cUnit);
-extern RegLocation getReturnLocWideAlt(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturnWideAlt(CompilationUnit *cUnit);
-extern RegLocation getReturnLoc(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturn(CompilationUnit *cUnit);
-extern RegLocation getReturnLocAlt(CompilationUnit *cUnit);
+extern RegLocation dvmCompilerGetReturnAlt(CompilationUnit *cUnit);
/* Clobber any temp associated with an sReg. Could be in either class */
-extern void clobberSReg(CompilationUnit *cUnit, int sReg);
+extern void dvmCompilerClobberSReg(CompilationUnit *cUnit, int sReg);
/* Return a temp if one is available, -1 otherwise */
-extern int allocFreeTemp(CompilationUnit *cUnit);
+extern int dvmCompilerAllocFreeTemp(CompilationUnit *cUnit);
/*
- * Similar to allocTemp(), but forces the allocation of a specific
+ * Similar to dvmCompilerAllocTemp(), but forces the allocation of a specific
* register. No check is made to see if the register was previously
* allocated. Use with caution.
*/
-extern void lockTemp(CompilationUnit *cUnit, int reg);
+extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg);
-extern RegLocation wideToNarrowLoc(CompilationUnit *cUnit, RegLocation rl);
+extern RegLocation dvmCompilerWideToNarrow(CompilationUnit *cUnit,
+ RegLocation rl);
/*
* Free all allocated temps in the temp pools. Note that this does
* not affect the "liveness" of a temp register, which will stay
* live until it is either explicitly killed or reallocated.
*/
-extern void resetRegPool(CompilationUnit *cUnit);
+extern void dvmCompilerResetRegPool(CompilationUnit *cUnit);
-extern void clobberAllRegs(CompilationUnit *cUnit);
+extern void dvmCompilerClobberAllRegs(CompilationUnit *cUnit);
-extern void resetDefTracking(CompilationUnit *cUnit);
+extern void dvmCompilerResetDefTracking(CompilationUnit *cUnit);
#include "Ralloc.h"
/*
- * FIXME - dvmCompiler prefixes are not added yet to routines exposed to the
- * code generator.
- */
-
-/*
* Register usage for 16-bit Thumb systems:
* r0-r3: Temp/argument
* lr(r14): Temp for translations, return address for handlers
* not affect the "liveness" of a temp register, which will stay
* live until it is either explicitly killed or reallocated.
*/
-extern void resetRegPool(CompilationUnit *cUnit)
+extern void dvmCompilerResetRegPool(CompilationUnit *cUnit)
{
int i;
for (i=0; i < cUnit->regPool->numCoreTemps; i++) {
}
/* Set up temp & preserved register pools specialized by target */
-extern void initPool(RegisterInfo *regs, int *regNums, int num)
+extern void dvmCompilerInitPool(RegisterInfo *regs, int *regNums, int num)
{
int i;
for (i=0; i < num; i++) {
if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) {
info1->dirty = false;
info2->dirty = false;
- if (sReg2vReg(cUnit, info2->sReg) < sReg2vReg(cUnit, info1->sReg))
+ if (dvmCompilerS2VReg(cUnit, info2->sReg) <
+ dvmCompilerS2VReg(cUnit, info1->sReg))
info1 = info2;
dvmCompilerFlushRegWideImpl(cUnit, rFP,
- sReg2vReg(cUnit, info1->sReg) << 2,
+ dvmCompilerS2VReg(cUnit, info1->sReg) << 2,
info1->reg, info1->partner);
}
}
RegisterInfo *info = getRegInfo(cUnit, reg);
if (info->live && info->dirty) {
info->dirty = false;
- dvmCompilerFlushRegImpl(cUnit, rFP, sReg2vReg(cUnit, info->sReg) << 2,
+ dvmCompilerFlushRegImpl(cUnit, rFP,
+ dvmCompilerS2VReg(cUnit, info->sReg) << 2,
reg, kWord);
}
}
}
/* Mark a temp register as dead. Does not affect allocation state. */
-void clobberReg(CompilationUnit *cUnit, int reg)
+void dvmCompilerClobber(CompilationUnit *cUnit, int reg)
{
if (!clobberRegBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps, reg)) {
}
/* Clobber any temp associated with an sReg. Could be in either class */
-extern void clobberSReg(CompilationUnit *cUnit, int sReg)
+extern void dvmCompilerClobberSReg(CompilationUnit *cUnit, int sReg)
{
clobberSRegBody(cUnit->regPool->coreTemps, cUnit->regPool->numCoreTemps,
sReg);
//Tuning: redo this to widen the live window on freed temps
for (i=0; i< numTemps; i++) {
if (!p[i].inUse && !p[i].live) {
- clobberReg(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
p[i].inUse = true;
p[i].pair = false;
return p[i].reg;
}
for (i=0; i< numTemps; i++) {
if (!p[i].inUse) {
- clobberReg(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
p[i].inUse = true;
p[i].pair = false;
return p[i].reg;
}
//REDO: too many assumptions.
-extern int allocTempDouble(CompilationUnit *cUnit)
+extern int dvmCompilerAllocTempDouble(CompilationUnit *cUnit)
{
RegisterInfo *p = cUnit->regPool->FPTemps;
int numTemps = cUnit->regPool->numFPTemps;
for (i=0; i < numTemps; i+=2) {
if ((!p[i].inUse && !p[i].live) &&
(!p[i+1].inUse && !p[i+1].live)) {
- clobberReg(cUnit, p[i].reg);
- clobberReg(cUnit, p[i+1].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i+1].reg);
p[i].inUse = true;
p[i+1].inUse = true;
assert((p[i].reg+1) == p[i+1].reg);
}
for (i=0; i < numTemps; i+=2) {
if (!p[i].inUse && !p[i+1].inUse) {
- clobberReg(cUnit, p[i].reg);
- clobberReg(cUnit, p[i+1].reg);
+ dvmCompilerClobber(cUnit, p[i].reg);
+ dvmCompilerClobber(cUnit, p[i+1].reg);
p[i].inUse = true;
p[i+1].inUse = true;
assert((p[i].reg+1) == p[i+1].reg);
}
/* Return a temp if one is available, -1 otherwise */
-extern int allocFreeTemp(CompilationUnit *cUnit)
+extern int dvmCompilerAllocFreeTemp(CompilationUnit *cUnit)
{
return allocTempBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps, true);
}
-extern int allocTemp(CompilationUnit *cUnit)
+extern int dvmCompilerAllocTemp(CompilationUnit *cUnit)
{
return allocTempBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps, true);
}
-extern int allocTempFloat(CompilationUnit *cUnit)
+extern int dvmCompilerAllocTempFloat(CompilationUnit *cUnit)
{
return allocTempBody(cUnit, cUnit->regPool->FPTemps,
cUnit->regPool->numFPTemps, true);
return res;
}
-extern void freeTemp(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerFreeTemp(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
}
//FIXME - this needs to also check the preserved pool.
-extern RegisterInfo *isLive(CompilationUnit *cUnit, int reg)
+extern RegisterInfo *dvmCompilerIsLive(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
return NULL;
}
-extern RegisterInfo *isTemp(CompilationUnit *cUnit, int reg)
+extern RegisterInfo *dvmCompilerIsTemp(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
}
/*
- * Similar to allocTemp(), but forces the allocation of a specific
+ * Similar to dvmCompilerAllocTemp(), but forces the allocation of a specific
* register. No check is made to see if the register was previously
* allocated. Use with caution.
*/
-extern void lockTemp(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerLockTemp(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = cUnit->regPool->coreTemps;
int numTemps = cUnit->regPool->numCoreTemps;
static void lockArgRegs(CompilationUnit *cUnit)
{
- lockTemp(cUnit, r0);
- lockTemp(cUnit, r1);
- lockTemp(cUnit, r2);
- lockTemp(cUnit, r3);
+ dvmCompilerLockTemp(cUnit, r0);
+ dvmCompilerLockTemp(cUnit, r1);
+ dvmCompilerLockTemp(cUnit, r2);
+ dvmCompilerLockTemp(cUnit, r3);
}
/* Clobber all regs that might be used by an external C call */
-extern void clobberCallRegs(CompilationUnit *cUnit)
+extern void dvmCompilerColbberCallRegs(CompilationUnit *cUnit)
{
- clobberReg(cUnit, r0);
- clobberReg(cUnit, r1);
- clobberReg(cUnit, r2);
- clobberReg(cUnit, r3);
- clobberReg(cUnit, r9); // Not sure we need to do this, be convervative
- clobberReg(cUnit, r11);
- clobberReg(cUnit, r12);
- clobberReg(cUnit, rlr);
+ dvmCompilerClobber(cUnit, r0);
+ dvmCompilerClobber(cUnit, r1);
+ dvmCompilerClobber(cUnit, r2);
+ dvmCompilerClobber(cUnit, r3);
+ dvmCompilerClobber(cUnit, r9); // Need to do this?, be convervative
+ dvmCompilerClobber(cUnit, r11);
+ dvmCompilerClobber(cUnit, r12);
+ dvmCompilerClobber(cUnit, rlr);
}
/* Clobber all of the temps that might be used by a handler. */
-extern void clobberHandlerRegs(CompilationUnit *cUnit)
+extern void dvmCompilerClobberHandlerRegs(CompilationUnit *cUnit)
{
//TUNING: reduce the set of regs used by handlers. Only a few need lots.
- clobberCallRegs(cUnit);
- clobberReg(cUnit, r4PC);
- clobberReg(cUnit, r9);
- clobberReg(cUnit, r10);
+ dvmCompilerColbberCallRegs(cUnit);
+ dvmCompilerClobber(cUnit, r4PC);
+ dvmCompilerClobber(cUnit, r9);
+ dvmCompilerClobber(cUnit, r10);
}
-extern void resetDef(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerResetDef(CompilationUnit *cUnit, int reg)
{
RegisterInfo *p = getRegInfo(cUnit, reg);
p->defStart = NULL;
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDef(CompilationUnit *cUnit, RegLocation rl,
+extern void dvmCompilerMarkDef(CompilationUnit *cUnit, RegLocation rl,
LIR *start, LIR *finish)
{
assert(!rl.wide);
* on entry start points to the LIR prior to the beginning of the
* sequence.
*/
-extern void markDefWide(CompilationUnit *cUnit, RegLocation rl,
+extern void dvmCompilerMarkDefWide(CompilationUnit *cUnit, RegLocation rl,
LIR *start, LIR *finish)
{
assert(rl.wide);
assert(start && start->next);
assert(finish);
RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
- resetDef(cUnit, rl.highReg); // Only track low of pair
+ dvmCompilerResetDef(cUnit, rl.highReg); // Only track low of pair
p->defStart = start->next;
p->defEnd = finish;
}
-extern RegLocation wideToNarrowLoc(CompilationUnit *cUnit, RegLocation rl)
+extern RegLocation dvmCompilerWideToNarrow(CompilationUnit *cUnit,
+ RegLocation rl)
{
assert(rl.wide);
if (rl.location == kLocPhysReg) {
return rl;
}
-extern void resetDefLoc(CompilationUnit *cUnit, RegLocation rl)
+extern void dvmCompilerResetDefLoc(CompilationUnit *cUnit, RegLocation rl)
{
assert(!rl.wide);
if (!(gDvmJit.disableOpt & (1 << kSuppressLoads))) {
nullifyRange(cUnit, p->defStart, p->defEnd,
p->sReg, rl.sRegLow);
}
- resetDef(cUnit, rl.lowReg);
+ dvmCompilerResetDef(cUnit, rl.lowReg);
}
-extern void resetDefLocWide(CompilationUnit *cUnit, RegLocation rl)
+extern void dvmCompilerResetDefLocWide(CompilationUnit *cUnit, RegLocation rl)
{
assert(rl.wide);
if (!(gDvmJit.disableOpt & (1 << kSuppressLoads))) {
nullifyRange(cUnit, p->defStart, p->defEnd,
p->sReg, rl.sRegLow);
}
- resetDef(cUnit, rl.lowReg);
- resetDef(cUnit, rl.highReg);
+ dvmCompilerResetDef(cUnit, rl.lowReg);
+ dvmCompilerResetDef(cUnit, rl.highReg);
}
-extern void resetDefTracking(CompilationUnit *cUnit)
+extern void dvmCompilerResetDefTracking(CompilationUnit *cUnit)
{
int i;
for (i=0; i< cUnit->regPool->numCoreTemps; i++) {
- resetDef(cUnit, cUnit->regPool->coreTemps[i].reg);
+ dvmCompilerResetDef(cUnit, cUnit->regPool->coreTemps[i].reg);
}
for (i=0; i< cUnit->regPool->numFPTemps; i++) {
- resetDef(cUnit, cUnit->regPool->FPTemps[i].reg);
+ dvmCompilerResetDef(cUnit, cUnit->regPool->FPTemps[i].reg);
}
}
-extern void clobberAllRegs(CompilationUnit *cUnit)
+extern void dvmCompilerClobberAllRegs(CompilationUnit *cUnit)
{
int i;
for (i=0; i< cUnit->regPool->numCoreTemps; i++) {
- clobberReg(cUnit, cUnit->regPool->coreTemps[i].reg);
+ dvmCompilerClobber(cUnit, cUnit->regPool->coreTemps[i].reg);
}
for (i=0; i< cUnit->regPool->numFPTemps; i++) {
- clobberReg(cUnit, cUnit->regPool->FPTemps[i].reg);
+ dvmCompilerClobber(cUnit, cUnit->regPool->FPTemps[i].reg);
}
}
/* To be used when explicitly managing register use */
-extern void lockAllTemps(CompilationUnit *cUnit)
+extern void dvmCompilerLockAllTemps(CompilationUnit *cUnit)
{
int i;
for (i=0; i< cUnit->regPool->numCoreTemps; i++) {
- lockTemp(cUnit, cUnit->regPool->coreTemps[i].reg);
+ dvmCompilerLockTemp(cUnit, cUnit->regPool->coreTemps[i].reg);
}
}
}
}
-extern void flushAllRegs(CompilationUnit *cUnit)
+extern void dvmCompilerFlushAllRegs(CompilationUnit *cUnit)
{
flushAllRegsBody(cUnit, cUnit->regPool->coreTemps,
cUnit->regPool->numCoreTemps);
flushAllRegsBody(cUnit, cUnit->regPool->FPTemps,
cUnit->regPool->numFPTemps);
- clobberAllRegs(cUnit);
+ dvmCompilerClobberAllRegs(cUnit);
}
}
}
-extern void markRegLive(CompilationUnit *cUnit, int reg, int sReg)
+extern void dvmCompilerMarkLive(CompilationUnit *cUnit, int reg, int sReg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
if ((info->reg == reg) && (info->sReg == sReg) && info->live) {
return; /* already live */
} else if (sReg != INVALID_SREG) {
- clobberSReg(cUnit, sReg);
+ dvmCompilerClobberSReg(cUnit, sReg);
info->live = true;
} else {
/* Can't be live if no associated sReg */
info->sReg = sReg;
}
-extern void markRegPair(CompilationUnit *cUnit, int lowReg, int highReg)
+extern void dvmCompilerMarkPair(CompilationUnit *cUnit, int lowReg, int highReg)
{
RegisterInfo *infoLo = getRegInfo(cUnit, lowReg);
RegisterInfo *infoHi = getRegInfo(cUnit, highReg);
info->pair = false;
}
-extern void markRegClean(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerMarkClean(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
info->dirty = false;
}
-extern void markRegDirty(CompilationUnit *cUnit, int reg)
+extern void dvmCompilerMarkDirty(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
info->dirty = true;
}
-extern void markRegInUse(CompilationUnit *cUnit, int reg)
+extern void dvmcompilerMarkInUse(CompilationUnit *cUnit, int reg)
{
RegisterInfo *info = getRegInfo(cUnit, reg);
info->inUse = true;
* is a bit complex when dealing with FP regs. Examine code to see
* if it's worthwhile trying to be more clever here.
*/
-extern RegLocation updateLoc(CompilationUnit *cUnit, RegLocation loc)
+extern RegLocation dvmCompilerUpdateLoc(CompilationUnit *cUnit, RegLocation loc)
{
assert(!loc.wide);
if (loc.location == kLocDalvikFrame) {
RegisterInfo *infoLo = allocLive(cUnit, loc.sRegLow, kAnyReg);
if (infoLo) {
if (infoLo->pair) {
- clobberReg(cUnit, infoLo->reg);
- clobberReg(cUnit, infoLo->partner);
+ dvmCompilerClobber(cUnit, infoLo->reg);
+ dvmCompilerClobber(cUnit, infoLo->partner);
} else {
loc.lowReg = infoLo->reg;
loc.location = kLocPhysReg;
}
/* see comments for updateLoc */
-extern RegLocation updateLocWide(CompilationUnit *cUnit, RegLocation loc)
+extern RegLocation dvmCompilerUpdateLocWide(CompilationUnit *cUnit,
+ RegLocation loc)
{
assert(loc.wide);
if (loc.location == kLocDalvikFrame) {
RegisterInfo *infoLo = allocLive(cUnit, loc.sRegLow, kAnyReg);
- RegisterInfo *infoHi = allocLive(cUnit, hiSReg(loc.sRegLow), kAnyReg);
+ RegisterInfo *infoHi = allocLive(cUnit,
+ dvmCompilerSRegHi(loc.sRegLow), kAnyReg);
bool match = true;
match = match && (infoLo != NULL);
match = match && (infoHi != NULL);
loc.lowReg = infoLo->reg;
loc.highReg = infoHi->reg;
loc.location = kLocPhysReg;
- markRegPair(cUnit, loc.lowReg, loc.highReg);
+ dvmCompilerMarkPair(cUnit, loc.lowReg, loc.highReg);
assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
return loc;
}
/* Can't easily reuse - just clobber any overlaps */
if (infoLo) {
- clobberReg(cUnit, infoLo->reg);
+ dvmCompilerClobber(cUnit, infoLo->reg);
if (infoLo->pair)
- clobberReg(cUnit, infoLo->partner);
+ dvmCompilerClobber(cUnit, infoLo->partner);
}
if (infoHi) {
- clobberReg(cUnit, infoHi->reg);
+ dvmCompilerClobber(cUnit, infoHi->reg);
if (infoHi->pair)
- clobberReg(cUnit, infoHi->partner);
+ dvmCompilerClobber(cUnit, infoHi->partner);
}
}
int lowReg;
int highReg;
- loc = updateLocWide(cUnit, loc);
+ loc = dvmCompilerUpdateLocWide(cUnit, loc);
/* If already in registers, we can assume proper form. Right reg class? */
if (loc.location == kLocPhysReg) {
loc.highReg);
copyRegInfo(cUnit, lowReg, loc.lowReg);
copyRegInfo(cUnit, highReg, loc.highReg);
- clobberReg(cUnit, loc.lowReg);
- clobberReg(cUnit, loc.highReg);
+ dvmCompilerClobber(cUnit, loc.lowReg);
+ dvmCompilerClobber(cUnit, loc.highReg);
loc.lowReg = lowReg;
loc.highReg = highReg;
- markRegPair(cUnit, loc.lowReg, loc.highReg);
+ dvmCompilerMarkPair(cUnit, loc.lowReg, loc.highReg);
assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
}
return loc;
assert((loc.location != kLocRetval) || (loc.sRegLow == INVALID_SREG));
assert((loc.location != kLocRetval) ||
- (hiSReg(loc.sRegLow) == INVALID_SREG));
+ (dvmCompilerSRegHi(loc.sRegLow) == INVALID_SREG));
newRegs = dvmCompilerAllocTypedTempPair(cUnit, loc.fp, regClass);
loc.lowReg = newRegs & 0xff;
loc.highReg = (newRegs >> 8) & 0xff;
- markRegPair(cUnit, loc.lowReg, loc.highReg);
+ dvmCompilerMarkPair(cUnit, loc.lowReg, loc.highReg);
if (update) {
loc.location = kLocPhysReg;
- markRegLive(cUnit, loc.lowReg, loc.sRegLow);
- markRegLive(cUnit, loc.highReg, hiSReg(loc.sRegLow));
+ dvmCompilerMarkLive(cUnit, loc.lowReg, loc.sRegLow);
+ dvmCompilerMarkLive(cUnit, loc.highReg, dvmCompilerSRegHi(loc.sRegLow));
}
assert(!FPREG(loc.lowReg) || ((loc.lowReg & 0x1) == 0));
return loc;
}
-extern RegLocation evalLoc(CompilationUnit *cUnit, RegLocation loc,
- int regClass, bool update)
+extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
+ int regClass, bool update)
{
RegisterInfo *infoLo = NULL;
int newReg;
if (loc.wide)
return evalLocWide(cUnit, loc, regClass, update);
- loc = updateLoc(cUnit, loc);
+ loc = dvmCompilerUpdateLoc(cUnit, loc);
if (loc.location == kLocPhysReg) {
if (!regClassMatches(regClass, loc.lowReg)) {
newReg = dvmCompilerAllocTypedTemp(cUnit, loc.fp, regClass);
dvmCompilerRegCopy(cUnit, newReg, loc.lowReg);
copyRegInfo(cUnit, newReg, loc.lowReg);
- clobberReg(cUnit, loc.lowReg);
+ dvmCompilerClobber(cUnit, loc.lowReg);
loc.lowReg = newReg;
}
return loc;
if (update) {
loc.location = kLocPhysReg;
- markRegLive(cUnit, loc.lowReg, loc.sRegLow);
+ dvmCompilerMarkLive(cUnit, loc.lowReg, loc.sRegLow);
}
return loc;
}
}
// Get the LocRecord associated with an SSA name use.
-extern RegLocation getSrcLoc(CompilationUnit *cUnit, MIR *mir, int num)
+extern RegLocation dvmCompilerGetSrc(CompilationUnit *cUnit, MIR *mir, int num)
{
- RegLocation loc = cUnit->regLocation[SREG(cUnit, getSrcSSAName(mir, num))];
- loc.fp = cUnit->regLocation[getSrcSSAName(mir, num)].fp;
+ RegLocation loc = cUnit->regLocation[
+ SREG(cUnit, dvmCompilerSSASrc(mir, num))];
+ loc.fp = cUnit->regLocation[dvmCompilerSSASrc(mir, num)].fp;
loc.wide = false;
return loc;
}
// Get the LocRecord associated with an SSA name def.
-extern RegLocation getDestLoc(CompilationUnit *cUnit, MIR *mir, int num)
+extern RegLocation dvmCompilerGetDest(CompilationUnit *cUnit, MIR *mir,
+ int num)
{
RegLocation loc = cUnit->regLocation[SREG(cUnit, getDestSSAName(mir, num))];
loc.fp = cUnit->regLocation[getDestSSAName(mir, num)].fp;
}
static RegLocation getLocWide(CompilationUnit *cUnit, MIR *mir,
- int low, int high, bool isSrc)
+ int low, int high, bool isSrc)
{
RegLocation lowLoc;
RegLocation highLoc;
/* Copy loc record for low word and patch in data from high word */
if (isSrc) {
- lowLoc = getSrcLoc(cUnit, mir, low);
- highLoc = getSrcLoc(cUnit, mir, high);
+ lowLoc = dvmCompilerGetSrc(cUnit, mir, low);
+ highLoc = dvmCompilerGetSrc(cUnit, mir, high);
} else {
- lowLoc = getDestLoc(cUnit, mir, low);
- highLoc = getDestLoc(cUnit, mir, high);
+ lowLoc = dvmCompilerGetDest(cUnit, mir, low);
+ highLoc = dvmCompilerGetDest(cUnit, mir, high);
}
/* Avoid this case by either promoting both or neither. */
assert(lowLoc.location == highLoc.location);
return lowLoc;
}
-extern RegLocation getDestLocWide(CompilationUnit *cUnit, MIR *mir,
- int low, int high)
+extern RegLocation dvmCompilerGetDestWide(CompilationUnit *cUnit, MIR *mir,
+ int low, int high)
{
return getLocWide(cUnit, mir, low, high, false);
}
-extern RegLocation getSrcLocWide(CompilationUnit *cUnit, MIR *mir,
+extern RegLocation dvmCompilerGetSrcWide(CompilationUnit *cUnit, MIR *mir,
int low, int high)
{
return getLocWide(cUnit, mir, low, high, true);
}
-extern RegLocation getReturnLocWide(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturnWide(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN_WIDE;
- clobberReg(cUnit, r0);
- clobberReg(cUnit, r1);
- markRegInUse(cUnit, r0);
- markRegInUse(cUnit, r1);
- markRegPair(cUnit, res.lowReg, res.highReg);
+ dvmCompilerClobber(cUnit, r0);
+ dvmCompilerClobber(cUnit, r1);
+ dvmcompilerMarkInUse(cUnit, r0);
+ dvmcompilerMarkInUse(cUnit, r1);
+ dvmCompilerMarkPair(cUnit, res.lowReg, res.highReg);
return res;
}
-extern RegLocation getReturnLocWideAlt(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturnWideAlt(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN_WIDE;
res.lowReg = r2;
res.highReg = r3;
- clobberReg(cUnit, r2);
- clobberReg(cUnit, r3);
- markRegInUse(cUnit, r2);
- markRegInUse(cUnit, r3);
- markRegPair(cUnit, res.lowReg, res.highReg);
+ dvmCompilerClobber(cUnit, r2);
+ dvmCompilerClobber(cUnit, r3);
+ dvmcompilerMarkInUse(cUnit, r2);
+ dvmcompilerMarkInUse(cUnit, r3);
+ dvmCompilerMarkPair(cUnit, res.lowReg, res.highReg);
return res;
}
-extern RegLocation getReturnLoc(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturn(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN;
- clobberReg(cUnit, r0);
- markRegInUse(cUnit, r0);
+ dvmCompilerClobber(cUnit, r0);
+ dvmcompilerMarkInUse(cUnit, r0);
return res;
}
-extern RegLocation getReturnLocAlt(CompilationUnit *cUnit)
+extern RegLocation dvmCompilerGetReturnAlt(CompilationUnit *cUnit)
{
RegLocation res = LOC_C_RETURN;
res.lowReg = r1;
- clobberReg(cUnit, r1);
- markRegInUse(cUnit, r1);
+ dvmCompilerClobber(cUnit, r1);
+ dvmcompilerMarkInUse(cUnit, r1);
return res;
}
/* Kill the corresponding bit in the null-checked register list */
-extern void killNullCheckedLocation(CompilationUnit *cUnit,
- RegLocation loc)
+extern void dvmCompilerKillNullCheckedLoc(CompilationUnit *cUnit,
+ RegLocation loc)
{
if (loc.location != kLocRetval) {
assert(loc.sRegLow != INVALID_SREG);
dvmClearBit(cUnit->regPool->nullCheckedRegs, loc.sRegLow);
if (loc.wide) {
- assert(hiSReg(loc.sRegLow) != INVALID_SREG);
- dvmClearBit(cUnit->regPool->nullCheckedRegs, hiSReg(loc.sRegLow));
+ assert(dvmCompilerSRegHi(loc.sRegLow) != INVALID_SREG);
+ dvmClearBit(cUnit->regPool->nullCheckedRegs,
+ dvmCompilerSRegHi(loc.sRegLow));
}
}
}
static ArmLIR *loadConstantValue(CompilationUnit *cUnit, int rDest, int value)
{
ArmLIR *res;
- int tDest = LOWREG(rDest) ? rDest : allocTemp(cUnit);
+ int tDest = LOWREG(rDest) ? rDest : dvmCompilerAllocTemp(cUnit);
/* See if the value can be constructed cheaply */
if ((value >= 0) && (value <= 255)) {
res = newLIR2(cUnit, kThumbMovImm, tDest, value);
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
- freeTemp(cUnit, tDest);
+ dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
} else if ((value & 0xFFFFFF00) == 0xFFFFFF00) {
newLIR2(cUnit, kThumbMvn, tDest, tDest);
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
- freeTemp(cUnit, tDest);
+ dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
}
}
if (rDest != tDest) {
opRegReg(cUnit, kOpMov, rDest, tDest);
- freeTemp(cUnit, tDest);
+ dvmCompilerFreeTemp(cUnit, tDest);
}
return res;
}
*/
static ArmLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
{
- if (isTemp(cUnit, rDest)) {
- clobberReg(cUnit, rDest);
- markRegInUse(cUnit, rDest);
+ if (dvmCompilerIsTemp(cUnit, rDest)) {
+ dvmCompilerClobber(cUnit, rDest);
+ dvmcompilerMarkInUse(cUnit, rDest);
}
return loadConstantValue(cUnit, rDest, value);
}
if (shortForm)
res = newLIR2(cUnit, opCode, rDestSrc1, absValue);
else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
if (op == kOpCmp)
newLIR2(cUnit, opCode, rDestSrc1, rScratch);
if (rDest == rSrc1) {
return opRegReg(cUnit, op, rDest, rSrc2);
} else if (rDest == rSrc2) {
- assert(isTemp(cUnit, rSrc1));
- clobberReg(cUnit, rSrc1);
+ assert(dvmCompilerIsTemp(cUnit, rSrc1));
+ dvmCompilerClobber(cUnit, rSrc1);
opRegReg(cUnit, op, rSrc1, rSrc2);
return opRegReg(cUnit, kOpMov, rDest, rSrc1);
} else {
case kOpOr:
case kOpXor:
if (rDest == rSrc1) {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
opRegReg(cUnit, op, rDest, rScratch);
} else {
res = loadConstant(cUnit, rDest, value);
newLIR3(cUnit, opCode, rDest, rSrc1, rDest);
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, value);
newLIR3(cUnit, opCode, rDest, rSrc1, rScratch);
}
int rNewIndex = rIndex;
if (scale) {
// Scale the index, but can't trash the original.
- rNewIndex = allocTemp(cUnit);
+ rNewIndex = dvmCompilerAllocTemp(cUnit);
first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
}
switch (size) {
res->branchInsertSV = true;
#endif
if (scale)
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
return (first) ? first : res;
}
ArmOpCode opCode = kThumbBkpt;
int rNewIndex = rIndex;
if (scale) {
- rNewIndex = allocTemp(cUnit);
+ rNewIndex = dvmCompilerAllocTemp(cUnit);
first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
}
switch (size) {
res->branchInsertSV = true;
#endif
if (scale)
- freeTemp(cUnit, rNewIndex);
+ dvmCompilerFreeTemp(cUnit, rNewIndex);
return (first) ? first : res;
}
}
} else {
if (pair) {
- int rTmp = allocFreeTemp(cUnit);
+ int rTmp = dvmCompilerAllocFreeTemp(cUnit);
if (rTmp < 0) {
//UNIMP: need to spill if no temps.
assert(0);
res = opRegRegImm(cUnit, kOpAdd, rTmp, rBase, displacement);
//TUNING: how to mark loadPair if Dalvik access?
loadPair(cUnit, rTmp, rDest, rDestHi);
- freeTemp(cUnit, rTmp);
+ dvmCompilerFreeTemp(cUnit, rTmp);
} else {
- int rTmp = (rBase == rDest) ? allocFreeTemp(cUnit) : rDest;
+ int rTmp = (rBase == rDest) ? dvmCompilerAllocFreeTemp(cUnit) : rDest;
if (rTmp < 0) {
//UNIMP: need to spill if no temps.
assert(0);
annotateDalvikRegAccess(load, displacement >> 2,
true /* isLoad */);
if (rTmp != rDest)
- freeTemp(cUnit, rTmp);
+ dvmCompilerFreeTemp(cUnit, rTmp);
}
}
#if defined(WITH_SELF_VERIFICATION)
store2 = newLIR3(cUnit, opCode, rSrcHi, rBase, encodedDisp + 1);
}
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
if (pair) {
//TUNING: how to mark storePair as Dalvik access if it is?
res = opRegRegImm(cUnit, kOpAdd, rScratch, rBase, displacement);
false /* isLoad */);
}
}
- freeTemp(cUnit, rScratch);
+ dvmCompilerFreeTemp(cUnit, rScratch);
}
#if defined(WITH_SELF_VERIFICATION)
if (store != NULL && cUnit->heapMemOp)
}
static void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
- int srcLo, int srcHi)
+ int srcLo, int srcHi)
{
// Handle overlap
if (srcHi == destLo) {
}
static inline ArmLIR *genRegImmCheck(CompilationUnit *cUnit,
- ArmConditionCode cond, int reg,
- int checkValue, int dOffset,
- ArmLIR *pcrLabel)
+ ArmConditionCode cond, int reg,
+ int checkValue, int dOffset,
+ ArmLIR *pcrLabel)
{
int tReg;
ArmLIR *res;
if ((checkValue & 0xff) != checkValue) {
- tReg = allocTemp(cUnit);
+ tReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, tReg, checkValue);
res = genRegRegCheck(cUnit, cond, reg, tReg, dOffset, pcrLabel);
- freeTemp(cUnit, tReg);
+ dvmCompilerFreeTemp(cUnit, tReg);
return res;
}
newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
{
RegLocation rlResult;
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegImm(cUnit, kOpAdd, rlResult.lowReg,
rlSrc.lowReg, 0x80000000);
storeValue(cUnit, rlDest, rlResult);
}
static void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest,
- RegLocation rlSrc)
+ RegLocation rlSrc)
{
RegLocation rlResult;
rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegImm(cUnit, kOpAdd, rlResult.highReg, rlSrc.highReg,
0x80000000);
genRegCopy(cUnit, rlResult.lowReg, rlSrc.lowReg);
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
genDispatchToHandler(cUnit, TEMPLATE_MUL_LONG);
- rlResult = getReturnLocWide(cUnit);
+ rlResult = dvmCompilerGetReturnWide(cUnit);
storeValueWide(cUnit, rlDest, rlResult);
}
opRegReg(cUnit, firstOp, rlSrc1.lowReg, rlResult.lowReg);
opRegReg(cUnit, secondOp, rlSrc1.highReg, rlResult.highReg);
// Old reg assignments are now invalid
- clobberReg(cUnit, rlResult.lowReg);
- clobberReg(cUnit, rlResult.highReg);
- clobberReg(cUnit, rlSrc1.lowReg);
- clobberReg(cUnit, rlSrc1.highReg);
+ dvmCompilerClobber(cUnit, rlResult.lowReg);
+ dvmCompilerClobber(cUnit, rlResult.highReg);
+ dvmCompilerClobber(cUnit, rlSrc1.lowReg);
+ dvmCompilerClobber(cUnit, rlSrc1.highReg);
rlDest.location = kLocDalvikFrame;
assert(rlSrc1.location == kLocPhysReg);
// Reassign registers - rlDest will now get rlSrc1's old regs
} else {
// Copy Src1 to Dest
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, false);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, false);
loadValueDirectWide(cUnit, rlSrc1, rlResult.lowReg,
rlResult.highReg);
rlResult.location = kLocPhysReg;
pool->coreRegs = NULL;
pool->numFPRegs = 0;
pool->FPRegs = NULL;
- initPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
- initPool(pool->FPTemps, NULL, 0);
- initPool(pool->coreRegs, NULL, 0);
- initPool(pool->FPRegs, NULL, 0);
+ dvmCompilerInitPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
+ dvmCompilerInitPool(pool->FPTemps, NULL, 0);
+ dvmCompilerInitPool(pool->coreRegs, NULL, 0);
+ dvmCompilerInitPool(pool->FPRegs, NULL, 0);
pool->nullCheckedRegs =
dvmCompilerAllocBitVector(cUnit->numSSARegs, false);
}
static ArmLIR *genExportPC(CompilationUnit *cUnit, MIR *mir)
{
ArmLIR *res;
- int rDPC = allocTemp(cUnit);
- int rAddr = allocTemp(cUnit);
+ int rDPC = dvmCompilerAllocTemp(cUnit);
+ int rAddr = dvmCompilerAllocTemp(cUnit);
int offset = offsetof(StackSaveArea, xtra.currentPc);
res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
newLIR2(cUnit, kThumbMovRR, rAddr, rFP);
loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
genDispatchToHandler(cUnit, TEMPLATE_CMP_LONG);
- rlResult = getReturnLoc(cUnit);
+ rlResult = dvmCompilerGetReturn(cUnit);
storeValue(cUnit, rlDest, rlResult);
}
{
DecodedInstruction *dInsn = &mir->dalvikInsn;
int offset = offsetof(InterpState, retval);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
int regObj = loadValue(cUnit, rlObj, kCoreReg).lowReg;
- int reg1 = allocTemp(cUnit);
- genNullCheck(cUnit, getSrcSSAName(mir, 0), regObj, mir->offset, NULL);
+ int reg1 = dvmCompilerAllocTemp(cUnit);
+ genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0), regObj, mir->offset, NULL);
loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_count, reg1);
storeWordDisp(cUnit, rGLUE, offset, reg1);
return false;
DecodedInstruction *dInsn = &mir->dalvikInsn;
int offset = offsetof(InterpState, retval);
int contents = offsetof(ArrayObject, contents);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlIdx = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
int regObj = loadValue(cUnit, rlObj, kCoreReg).lowReg;
int regIdx = loadValue(cUnit, rlIdx, kCoreReg).lowReg;
- int regMax = allocTemp(cUnit);
- int regOff = allocTemp(cUnit);
- ArmLIR * pcrLabel = genNullCheck(cUnit, getSrcSSAName(mir, 0),
+ int regMax = dvmCompilerAllocTemp(cUnit);
+ int regOff = dvmCompilerAllocTemp(cUnit);
+ ArmLIR * pcrLabel = genNullCheck(cUnit, dvmCompilerSSASrc(mir, 0),
regObj, mir->offset, NULL);
loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_count, regMax);
loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_offset, regOff);
newLIR3(cUnit, kThumbAddRRR, regIdx, regIdx, regOff);
newLIR3(cUnit, kThumbAddRRR, regIdx, regIdx, regIdx);
newLIR3(cUnit, kThumbLdrhRRR, regMax, regObj, regIdx);
- freeTemp(cUnit, regOff);
+ dvmCompilerFreeTemp(cUnit, regOff);
storeWordDisp(cUnit, rGLUE, offset, regMax);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, regObj);
- clobberReg(cUnit, regIdx);
+ dvmCompilerClobber(cUnit, regObj);
+ dvmCompilerClobber(cUnit, regIdx);
return false;
}
static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg;
- int sign = allocTemp(cUnit);
+ int sign = dvmCompilerAllocTemp(cUnit);
/* abs(x) = y<=x>>31, (x+y)^y. Shorter in ARM/THUMB2, no skip in THUMB */
newLIR3(cUnit, kThumbAsrRRI5, sign, reg0, 31);
newLIR3(cUnit, kThumbAddRRR, reg0, reg0, sign);
newLIR2(cUnit, kThumbEorRR, reg0, sign);
- freeTemp(cUnit, sign);
+ dvmCompilerFreeTemp(cUnit, sign);
storeWordDisp(cUnit, rGLUE, offset, reg0);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, reg0);
+ dvmCompilerClobber(cUnit, reg0);
return false;
}
static bool genInlinedAbsFloat(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
int reg0 = loadValue(cUnit, rlSrc, kCoreReg).lowReg;
- int signMask = allocTemp(cUnit);
+ int signMask = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, signMask, 0x7fffffff);
newLIR2(cUnit, kThumbAndRR, reg0, signMask);
- freeTemp(cUnit, signMask);
+ dvmCompilerFreeTemp(cUnit, signMask);
storeWordDisp(cUnit, rGLUE, offset, reg0);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, reg0);
+ dvmCompilerClobber(cUnit, reg0);
return true;
}
static bool genInlinedAbsDouble(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation regSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
int reglo = regSrc.lowReg;
int reghi = regSrc.highReg;
- int signMask = allocTemp(cUnit);
+ int signMask = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, signMask, 0x7fffffff);
storeWordDisp(cUnit, rGLUE, offset, reglo);
newLIR2(cUnit, kThumbAndRR, reghi, signMask);
- freeTemp(cUnit, signMask);
+ dvmCompilerFreeTemp(cUnit, signMask);
storeWordDisp(cUnit, rGLUE, offset + 4, reghi);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, reghi);
+ dvmCompilerClobber(cUnit, reghi);
return true;
}
static bool genInlinedMinMaxInt(CompilationUnit *cUnit, MIR *mir, bool isMin)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc1 = getSrcLoc(cUnit, mir, 0);
- RegLocation rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
int reg0 = loadValue(cUnit, rlSrc1, kCoreReg).lowReg;
int reg1 = loadValue(cUnit, rlSrc2, kCoreReg).lowReg;
newLIR2(cUnit, kThumbCmpRR, reg0, reg1);
newLIR3(cUnit, kThumbStrRRI5, reg0, rGLUE, offset >> 2);
branch1->generic.target = (LIR *)target;
//FIXME: rewrite this to not clobber
- clobberReg(cUnit,reg0);
+ dvmCompilerClobber(cUnit,reg0);
return false;
}
static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
{
int offset = offsetof(InterpState, retval);
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation regSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
int oplo = regSrc.lowReg;
int ophi = regSrc.highReg;
- int sign = allocTemp(cUnit);
+ int sign = dvmCompilerAllocTemp(cUnit);
/* abs(x) = y<=x>>31, (x+y)^y. Shorter in ARM/THUMB2, no skip in THUMB */
newLIR3(cUnit, kThumbAsrRRI5, sign, ophi, 31);
newLIR3(cUnit, kThumbAddRRR, oplo, oplo, sign);
newLIR2(cUnit, kThumbAdcRR, ophi, sign);
newLIR2(cUnit, kThumbEorRR, oplo, sign);
newLIR2(cUnit, kThumbEorRR, ophi, sign);
- freeTemp(cUnit, sign);
+ dvmCompilerFreeTemp(cUnit, sign);
storeWordDisp(cUnit, rGLUE, offset, oplo);
storeWordDisp(cUnit, rGLUE, offset + 4, ophi);
//FIXME: rewrite this to not clobber
- clobberReg(cUnit, oplo);
- clobberReg(cUnit, ophi);
+ dvmCompilerClobber(cUnit, oplo);
+ dvmCompilerClobber(cUnit, ophi);
return false;
}
int highReg;
int lowReg;
int res = 0;
- lowReg = allocTemp(cUnit);
- highReg = allocTemp(cUnit);
+ lowReg = dvmCompilerAllocTemp(cUnit);
+ highReg = dvmCompilerAllocTemp(cUnit);
res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
return res;
}
int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
{
- return allocTemp(cUnit);
+ return dvmCompilerAllocTemp(cUnit);
}
static int coreTemps[] = {r0, r1, r2, r3, r4PC, r7, r8, r9, r10, r11, r12};
static int corePreserved[] = {};
static int fpTemps[] = {fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
- fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31};
+ fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31};
static int fpPreserved[] = {};
static int encodeImmSingle(int value)
*/
static ArmLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
{
- if (isTemp(cUnit, rDest)) {
- clobberReg(cUnit, rDest);
- markRegInUse(cUnit, rDest);
+ if (dvmCompilerIsTemp(cUnit, rDest)) {
+ dvmCompilerClobber(cUnit, rDest);
+ dvmcompilerMarkInUse(cUnit, rDest);
}
return loadConstantValue(cUnit, rDest, value);
}
if (modImm >= 0) {
res = newLIR2(cUnit, kThumb2CmpRI8, rSrc1, modImm);
} else {
- int rTmp = allocTemp(cUnit);
+ int rTmp = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rTmp, value);
opRegReg(cUnit, kOpCmp, rSrc1, rTmp);
- freeTemp(cUnit, rTmp);
+ dvmCompilerFreeTemp(cUnit, rTmp);
}
return res;
}
if (modImm >= 0) {
return newLIR3(cUnit, opCode, rDest, rSrc1, modImm);
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, rScratch, value);
if (EncodingMap[altOpCode].flags & IS_QUAD_OP)
res = newLIR4(cUnit, altOpCode, rDest, rSrc1, rScratch, 0);
else
res = newLIR3(cUnit, altOpCode, rDest, rSrc1, rScratch);
- freeTemp(cUnit, rScratch);
+ dvmCompilerFreeTemp(cUnit, rScratch);
return res;
}
}
switch (size) {
case kSingle:
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
if (scale) {
newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
encodeShift(kArmLsl, scale));
switch (size) {
case kSingle:
- regPtr = allocTemp(cUnit);
+ regPtr = dvmCompilerAllocTemp(cUnit);
if (scale) {
newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
encodeShift(kArmLsl, scale));
if (shortForm) {
load = res = newLIR3(cUnit, opCode, rDest, rBase, encodedDisp);
} else {
- int regOffset = allocTemp(cUnit);
+ int regOffset = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, regOffset, encodedDisp);
load = loadBaseIndexed(cUnit, rBase, regOffset, rDest, 0, size);
- freeTemp(cUnit, regOffset);
+ dvmCompilerFreeTemp(cUnit, regOffset);
}
if (rBase == rFP) {
}
static ArmLIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
- int displacement, int rDestLo, int rDestHi,
- int sReg)
+ int displacement, int rDestLo, int rDestHi,
+ int sReg)
{
return loadBaseDispBody(cUnit, mir, rBase, displacement, rDestLo, rDestHi,
kLong, sReg);
static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
- int displacement, int rSrc, int rSrcHi,
- OpSize size)
+ int displacement, int rSrc, int rSrcHi,
+ OpSize size)
{
ArmLIR *res, *store;
ArmOpCode opCode = kThumbBkpt;
if (shortForm) {
store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp);
} else {
- int rScratch = allocTemp(cUnit);
+ int rScratch = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rScratch, encodedDisp);
store = storeBaseIndexed(cUnit, rBase, rScratch, rSrc, 0, size);
- freeTemp(cUnit, rScratch);
+ dvmCompilerFreeTemp(cUnit, rScratch);
}
if (rBase == rFP) {
* satisfies.
*/
static ArmLIR *genRegImmCheck(CompilationUnit *cUnit,
- ArmConditionCode cond, int reg,
- int checkValue, int dOffset,
- ArmLIR *pcrLabel)
+ ArmConditionCode cond, int reg,
+ int checkValue, int dOffset,
+ ArmLIR *pcrLabel)
{
ArmLIR *branch;
int modImm;
} else if (modImm >= 0) {
newLIR2(cUnit, kThumb2CmpRI8, reg, modImm);
} else {
- int tReg = allocTemp(cUnit);
+ int tReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, tReg, checkValue);
opRegReg(cUnit, kOpCmp, reg, tReg);
}
{
RegLocation rlResult;
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vnegs, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
}
static void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest,
- RegLocation rlSrc)
+ RegLocation rlSrc)
{
RegLocation rlResult;
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vnegd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc.lowReg, rlSrc.highReg));
storeValueWide(cUnit, rlDest, rlResult);
RegLocation rlSrc1, RegLocation rlSrc2)
{
RegLocation rlResult;
- int resLo = allocTemp(cUnit);
- int resHi = allocTemp(cUnit);
- int tmp1 = allocTemp(cUnit);
+ int resLo = dvmCompilerAllocTemp(cUnit);
+ int resHi = dvmCompilerAllocTemp(cUnit);
+ int tmp1 = dvmCompilerAllocTemp(cUnit);
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
newLIR4(cUnit, kThumb2Umull, resLo, resHi, rlSrc2.lowReg, rlSrc1.lowReg);
newLIR4(cUnit, kThumb2Mla, tmp1, rlSrc1.lowReg, rlSrc2.highReg, tmp1);
newLIR4(cUnit, kThumb2AddRRR, resHi, tmp1, resHi, 0);
- freeTemp(cUnit, tmp1);
+ dvmCompilerFreeTemp(cUnit, tmp1);
- rlResult = getReturnLocWide(cUnit); // Just as a template, will patch
+ rlResult = dvmCompilerGetReturnWide(cUnit); // Just as a template, will patch
rlResult.lowReg = resLo;
rlResult.highReg = resHi;
storeValueWide(cUnit, rlDest, rlResult);
RegLocation rlResult;
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegRegReg(cUnit, firstOp, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
opRegRegReg(cUnit, secondOp, rlResult.highReg, rlSrc1.highReg,
rlSrc2.highReg);
pool->coreRegs = NULL;
pool->numFPRegs = 0;
pool->FPRegs = NULL;
- initPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
- initPool(pool->FPTemps, fpTemps, pool->numFPTemps);
- initPool(pool->coreRegs, NULL, 0);
- initPool(pool->FPRegs, NULL, 0);
+ dvmCompilerInitPool(pool->coreTemps, coreTemps, pool->numCoreTemps);
+ dvmCompilerInitPool(pool->FPTemps, fpTemps, pool->numFPTemps);
+ dvmCompilerInitPool(pool->coreRegs, NULL, 0);
+ dvmCompilerInitPool(pool->FPRegs, NULL, 0);
pool->nullCheckedRegs =
dvmCompilerAllocBitVector(cUnit->numSSARegs, false);
}
{
ArmLIR *res;
int offset = offsetof(StackSaveArea, xtra.currentPc);
- int rDPC = allocTemp(cUnit);
+ int rDPC = dvmCompilerAllocTemp(cUnit);
res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
newLIR3(cUnit, kThumb2StrRRI8Predec, rDPC, rFP,
sizeof(StackSaveArea) - offset);
- freeTemp(cUnit, rDPC);
+ dvmCompilerFreeTemp(cUnit, rDPC);
return res;
}
*/
static void genMonitor(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
bool enter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER);
ArmLIR *target;
ArmLIR *branch;
assert(LW_SHAPE_THIN == 0);
loadValueDirectFixed(cUnit, rlSrc, r1); // Get obj
- lockAllTemps(cUnit); // Prepare for explicit register usage
- freeTemp(cUnit, r4PC); // Free up r4 for general use
+ dvmCompilerLockAllTemps(cUnit); // Prepare for explicit register usage
+ dvmCompilerFreeTemp(cUnit, r4PC); // Free up r4 for general use
loadWordDisp(cUnit, rGLUE, offsetof(InterpState, self), r0); // Get self
genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
loadWordDisp(cUnit, r0, offsetof(Thread, threadId), r3); // Get threadId
sizeof(StackSaveArea) -
offsetof(StackSaveArea, xtra.currentPc));
opReg(cUnit, kOpBlx, r7);
- clobberCallRegs(cUnit);
+ dvmCompilerColbberCallRegs(cUnit);
}
// Resume here
ArmLIR *target2;
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg);
- rlTemp.lowReg = allocTemp(cUnit);
+ rlTemp.lowReg = dvmCompilerAllocTemp(cUnit);
loadConstant(cUnit, rlTemp.lowReg, -1);
opRegReg(cUnit, kOpCmp, rlSrc1.highReg, rlSrc2.highReg);
ArmLIR *branch1 = opCondBranch(cUnit, kArmCondLt);
static bool genInlinedStringLength(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
rlObj = loadValue(cUnit, rlObj, kCoreReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, mir->offset, NULL);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count,
rlResult.lowReg);
static bool genInlinedStringCharAt(CompilationUnit *cUnit, MIR *mir)
{
int contents = offsetof(ArrayObject, contents);
- RegLocation rlObj = getSrcLoc(cUnit, mir, 0);
- RegLocation rlIdx = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlObj = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlIdx = dvmCompilerGetSrc(cUnit, mir, 1);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
RegLocation rlResult;
rlObj = loadValue(cUnit, rlObj, kCoreReg);
rlIdx = loadValue(cUnit, rlIdx, kCoreReg);
- int regMax = allocTemp(cUnit);
- int regOff = allocTemp(cUnit);
- int regPtr = allocTemp(cUnit);
+ int regMax = dvmCompilerAllocTemp(cUnit);
+ int regOff = dvmCompilerAllocTemp(cUnit);
+ int regPtr = dvmCompilerAllocTemp(cUnit);
ArmLIR *pcrLabel = genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg,
mir->offset, NULL);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_count, regMax);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_offset, regOff);
loadWordDisp(cUnit, rlObj.lowReg, gDvm.offJavaLangString_value, regPtr);
genBoundsCheck(cUnit, rlIdx.lowReg, regMax, mir->offset, pcrLabel);
- freeTemp(cUnit, regMax);
+ dvmCompilerFreeTemp(cUnit, regMax);
opRegImm(cUnit, kOpAdd, regPtr, contents);
opRegReg(cUnit, kOpAdd, regOff, rlIdx.lowReg);
- rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
loadBaseIndexed(cUnit, regPtr, regOff, rlResult.lowReg, 1, kUnsignedHalf);
storeValue(cUnit, rlDest, rlResult);
return false;
static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kCoreReg);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);;
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
- int signReg = allocTemp(cUnit);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
+ int signReg = dvmCompilerAllocTemp(cUnit);
/*
* abs(x) = y<=x>>31, (x+y)^y.
* Thumb2's IT block also yields 3 instructions, but imposes
static bool genInlinedAbsFloat(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLoc(cUnit, mir, 0);
+ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
RegLocation rlDest = inlinedTarget(cUnit, mir, true);
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vabss, rlResult.lowReg, rlSrc.lowReg);
storeValue(cUnit, rlDest, rlResult);
return true;
static bool genInlinedAbsDouble(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, true);
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kFPReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, kThumb2Vabsd, S2D(rlResult.lowReg, rlResult.highReg),
S2D(rlSrc.lowReg, rlSrc.highReg));
storeValueWide(cUnit, rlDest, rlResult);
static bool genInlinedMinMaxInt(CompilationUnit *cUnit, MIR *mir, bool isMin)
{
- RegLocation rlSrc1 = getSrcLoc(cUnit, mir, 0);
- RegLocation rlSrc2 = getSrcLoc(cUnit, mir, 1);
+ RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0);
+ RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1);
rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg);
RegLocation rlDest = inlinedTarget(cUnit, mir, false);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg);
genIT(cUnit, (isMin) ? kArmCondGt : kArmCondLt, "E");
opRegReg(cUnit, kOpMov, rlResult.lowReg, rlSrc2.lowReg);
static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
{
- RegLocation rlSrc = getSrcLocWide(cUnit, mir, 0, 1);
+ RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
RegLocation rlDest = inlinedTargetWide(cUnit, mir, false);
rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
- RegLocation rlResult = evalLoc(cUnit, rlDest, kCoreReg, true);
- int signReg = allocTemp(cUnit);
+ RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true);
+ int signReg = dvmCompilerAllocTemp(cUnit);
/*
* abs(x) = y<=x>>31, (x+y)^y.
* Thumb2 IT block allows slightly shorter sequence,
int lowReg;
int res = 0;
if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg)) {
- lowReg = allocTempDouble(cUnit);
+ lowReg = dvmCompilerAllocTempDouble(cUnit);
highReg = lowReg + 1;
} else {
- lowReg = allocTemp(cUnit);
- highReg = allocTemp(cUnit);
+ lowReg = dvmCompilerAllocTemp(cUnit);
+ highReg = dvmCompilerAllocTemp(cUnit);
}
res = (lowReg & 0xff) | ((highReg & 0xff) << 8);
return res;
int regClass)
{
if (((regClass == kAnyReg) && fpHint) || (regClass == kFPReg))
- return allocTempFloat(cUnit);
- return allocTemp(cUnit);
+ return dvmCompilerAllocTempFloat(cUnit);
+ return dvmCompilerAllocTemp(cUnit);
}
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