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80 col violation.
author
Evan Cheng
<evan.cheng@apple.com>
Sat, 25 Jul 2009 01:55:25 +0000
(
01:55
+0000)
committer
Evan Cheng
<evan.cheng@apple.com>
Sat, 25 Jul 2009 01:55:25 +0000
(
01:55
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMBaseRegisterInfo.cpp
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diff --git
a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index
6b0692c
..
2405bd0
100644
(file)
--- a/
lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/
lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@
-959,7
+959,8
@@
void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
// Build the new ADD / SUB.
- BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
+ unsigned Opc = TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri);
+ BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
.addReg(BaseReg, RegState::Kill).addImm(ThisVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg;