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* desc-cpu.scm (cgen-desc.h): Tweak logit message for consistency.
authordevans <devans>
Sat, 20 Jun 2009 21:34:28 +0000 (21:34 +0000)
committerdevans <devans>
Sat, 20 Jun 2009 21:34:28 +0000 (21:34 +0000)
(cgen-desc.c): Ditto.
* sid-cpu.scm (cgen-desc.h, cgen-cpu.h, cgen-defs.h): Ditto.
(cgen-write.cxx, cgen-semantics.cxx, cgen-sem-switch.cxx): Ditto.
* sid-decode.scm (cgen-decode.h, cgen-decode.cxx): Ditto.
* sid-model.scm (cgen-model.cxx, cgen-model.h): Ditto.
* sim-arch.scm (cgen-arch.h, cgen-arch.c): Ditto.
(cgen-cpuall.h, cgen-ops.c): Ditto.
* sim-cpu.scm (cgen-cpu.h, cgen-defs.h, cgen-cpu.c): Ditto.
(cgen-read.c, cgen-write.c, cgen-semantics.c): Ditto.
(cgen-sem-switch.c): Ditto.
* sim-decode.scm (cgen-decode.h, cgen-decode.c): Ditto.
* sim-model.c (cgen-model.c): Ditto.

cgen/ChangeLog patch | blob | history
cgen/desc-cpu.scm patch | blob | history
cgen/sid-cpu.scm patch | blob | history
cgen/sid-decode.scm patch | blob | history
cgen/sid-model.scm patch | blob | history
cgen/sim-arch.scm patch | blob | history
cgen/sim-cpu.scm patch | blob | history
cgen/sim-decode.scm patch | blob | history
cgen/sim-model.scm patch | blob | history

diff --git a/cgen/ChangeLog b/cgen/ChangeLog
index a36fd07..bdfb76e 100644 (file)
--- a/cgen/ChangeLog
+++ b/cgen/ChangeLog
@@ -1,3 +1,20 @@
+2009-06-20  Masaki Muranaka  <monaka@monami-software.com>
+           Doug Evans  <dje@sebabeach.org>
+
+       * desc-cpu.scm (cgen-desc.h): Tweak logit message for consistency.
+       (cgen-desc.c): Ditto.
+       * sid-cpu.scm (cgen-desc.h, cgen-cpu.h, cgen-defs.h): Ditto.
+       (cgen-write.cxx, cgen-semantics.cxx, cgen-sem-switch.cxx): Ditto.
+       * sid-decode.scm (cgen-decode.h, cgen-decode.cxx): Ditto.
+       * sid-model.scm (cgen-model.cxx, cgen-model.h): Ditto.
+       * sim-arch.scm (cgen-arch.h, cgen-arch.c): Ditto.
+       (cgen-cpuall.h, cgen-ops.c): Ditto.
+       * sim-cpu.scm (cgen-cpu.h, cgen-defs.h, cgen-cpu.c): Ditto.
+       (cgen-read.c, cgen-write.c, cgen-semantics.c): Ditto.
+       (cgen-sem-switch.c): Ditto.
+       * sim-decode.scm (cgen-decode.h, cgen-decode.c): Ditto.
+       * sim-model.c (cgen-model.c): Ditto.
+
 2009-06-18  Doug Evans  <dje@sebabeach.org>
 
        * gen-all-doc: Add fr30, ip2k, iq2000, lm32, mep, mt.
diff --git a/cgen/desc-cpu.scm b/cgen/desc-cpu.scm
index c716f61..872436e 100644 (file)
--- a/cgen/desc-cpu.scm
+++ b/cgen/desc-cpu.scm
@@ -965,7 +965,7 @@ init_tables (void)
 ; Then they'd be usable and we wouldn't have to special case them here.
 
 (define (cgen-desc.h)
-  (logit 1 "Generating " (current-arch-name) " desc.h ...\n")
+  (logit 1 "Generating " (current-arch-name) "-desc.h ...\n")
   (string-write
    (gen-c-copyright "CPU data header for @arch@."
                  CURRENT-COPYRIGHT CURRENT-PACKAGE)
@@ -1018,7 +1018,7 @@ init_tables (void)
 ; no place to put this file.  To be revisited when we do have such a place.
 
 (define (cgen-desc.c)
-  (logit 1 "Generating " (current-arch-name) " desc.c ...\n")
+  (logit 1 "Generating " (current-arch-name) "-desc.c ...\n")
   (string-write
    (gen-c-copyright "CPU data for @arch@."
                  CURRENT-COPYRIGHT CURRENT-PACKAGE)
diff --git a/cgen/sid-cpu.scm b/cgen/sid-cpu.scm
index d81218d..f3c23ff 100644 (file)
--- a/cgen/sid-cpu.scm
+++ b/cgen/sid-cpu.scm
@@ -71,7 +71,7 @@
 ; Generate <cpu>-desc.h.
 
 (define (cgen-desc.h)
-  (logit 1 "Generating " (gen-cpu-name) " desc.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-desc.h ...\n")
 
   (string-write
    (gen-c-copyright "Misc. entries in the @arch@ description file."
@@ -287,7 +287,7 @@ namespace @arch@ {
 ; Generate <cpu>-cpu.h
 
 (define (cgen-cpu.h)
-  (logit 1 "Generating " (gen-cpu-name) " cpu.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-cpu.h ...\n")
   (assert-keep-one)
 
   ; Turn parallel execution support on if cpu needs it.
@@ -545,7 +545,7 @@ typedef struct @prefix@_trace_record {
 ; Generate <cpu>-defs.h
 
 (define (cgen-defs.h)
-  (logit 1 "Generating " (gen-cpu-name) " defs.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-defs.h ...\n")
   (assert-keep-one)
 
   ; Turn parallel execution support on if cpu needs it.
@@ -672,7 +672,7 @@ using namespace cgen;
 ")))
 
 (define (cgen-write.cxx)
-  (logit 1 "Generating " (gen-cpu-name) " write.cxx ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-write.cxx ...\n")
   (assert-keep-one)
 
   (sim-analyze-insns!)
@@ -784,7 +784,7 @@ using namespace cgen;
 ; Each instruction is implemented in its own function.
 
 (define (cgen-semantics.cxx)
-  (logit 1 "Generating " (gen-cpu-name) " semantics.cxx ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-semantics.cxx ...\n")
   (assert-keep-one)
 
   (sim-analyze-insns!)
@@ -1408,7 +1408,7 @@ restart:
 ; Generate sem-switch.cxx.
 
 (define (cgen-sem-switch.cxx)
-  (logit 1 "Generating " (gen-cpu-name) " sem-switch.cxx ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-sem-switch.cxx ...\n")
 
   (sim-analyze-insns!)
   (if (with-sem-frags?)
diff --git a/cgen/sid-decode.scm b/cgen/sid-decode.scm
index 698eebe..7382ba7 100644 (file)
--- a/cgen/sid-decode.scm
+++ b/cgen/sid-decode.scm
@@ -667,7 +667,7 @@ void
 ; Entry point.  Generate decode.h.
 
 (define (cgen-decode.h)
-  (logit 1 "Generating " (gen-cpu-name) " decode.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-decode.h ...\n")
 
   (sim-analyze-insns!)
 
@@ -723,7 +723,7 @@ typedef UINT @prefix@_insn_word;
 ; Entry point.  Generate decode.cxx.
 
 (define (cgen-decode.cxx)
-  (logit 1 "Generating " (gen-cpu-name) " decode.cxx ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-decode.cxx ...\n")
 
   (sim-analyze-insns!)
 
diff --git a/cgen/sid-model.scm b/cgen/sid-model.scm
index a382996..8d27034 100644 (file)
--- a/cgen/sid-model.scm
+++ b/cgen/sid-model.scm
@@ -487,7 +487,7 @@ const MACH " (gen-sym mach) "_mach =
 ; Generate model.cxx
 
 (define (cgen-model.cxx)
-  (logit 1 "Generating " (gen-cpu-name) " model.cxx ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-model.cxx ...\n")
   (assert-keep-one)
 
   ; Turn parallel execution support on if cpu needs it.
@@ -520,7 +520,7 @@ using namespace @cpu@; // FIXME: namespace organization still wip
 )
 
 (define (cgen-model.h)
-  (logit 1 "Generating " (gen-cpu-name) " model.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "-model.h ...\n")
   (assert-keep-one)
 
   (string-write
diff --git a/cgen/sim-arch.scm b/cgen/sim-arch.scm
index c25211b..45335bd 100644 (file)
--- a/cgen/sim-arch.scm
+++ b/cgen/sim-arch.scm
@@ -91,7 +91,7 @@
 ; It is intended to be included before sim-basics.h and sim-base.h.
 
 (define (cgen-arch.h)
-  (logit 1 "Generating arch.h ...\n")
+  (logit 1 "Generating " (current-arch-name) "'s arch.h ...\n")
 
   (string-write
    (gen-c-copyright "Simulator header for @arch@."
@@ -116,7 +116,7 @@
 ; This file defines non cpu family specific data about the architecture.
 
 (define (cgen-arch.c)
-  (logit 1 "Generating arch.c ...\n")
+  (logit 1 "Generating " (current-arch-name) "'s arch.c ...\n")
 
   (string-write
    (gen-c-copyright "Simulator support for @arch@."
@@ -135,7 +135,7 @@
 ; It is intended to be included after sim-base.h/cgen-sim.h.
 
 (define (cgen-cpuall.h)
-  (logit 1 "Generating cpuall.h ...\n")
+  (logit 1 "Generating " (current-arch-name) "'s cpuall.h ...\n")
 
   (string-write
    (gen-c-copyright "Simulator CPU header for @arch@."
@@ -154,7 +154,7 @@
 ; No longer used.
 
 (define (cgen-ops.c)
-  (logit 1 "Generating ops.c ...\n")
+  (logit 1 "Generating " (current-arch-name) "'s ops.c ...\n")
 
   (string-write
    (gen-c-copyright "Simulator operational support for @arch@."
diff --git a/cgen/sim-cpu.scm b/cgen/sim-cpu.scm
index 1a16470..0588e04 100644 (file)
--- a/cgen/sim-cpu.scm
+++ b/cgen/sim-cpu.scm
@@ -800,7 +800,7 @@ SEM_FN_NAME (@prefix@,init_idesc_table) (SIM_CPU *current_cpu)
 ; Generate cpu-<cpu>.h
 
 (define (cgen-cpu.h)
-  (logit 1 "Generating " (gen-cpu-name) " cpu.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s cpu.h ...\n")
 
   (sim-analyze-insns!)
 
@@ -843,7 +843,7 @@ SEM_FN_NAME (@prefix@,init_idesc_table) (SIM_CPU *current_cpu)
 ; Generate defs-<isa>.h.
 
 (define (cgen-defs.h)
-  (logit 1 "Generating " (obj:name (current-isa)) " defs.h ...\n")
+  (logit 1 "Generating " (obj:name (current-isa)) "'s defs.h ...\n")
 
   (sim-analyze-insns!)
 
@@ -874,7 +874,7 @@ SEM_FN_NAME (@prefix@,init_idesc_table) (SIM_CPU *current_cpu)
 ; Generate cpu-<cpu>.c
 
 (define (cgen-cpu.c)
-  (logit 1 "Generating " (gen-cpu-name) " cpu.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s cpu.c ...\n")
 
   (sim-analyze-insns!)
 
@@ -903,7 +903,7 @@ SEM_FN_NAME (@prefix@,init_idesc_table) (SIM_CPU *current_cpu)
 ; Generate read.c
 
 (define (cgen-read.c)
-  (logit 1 "Generating " (gen-cpu-name) " read.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s read.c ...\n")
 
   (sim-analyze-insns!)
 
@@ -981,7 +981,7 @@ SEM_FN_NAME (@prefix@,init_idesc_table) (SIM_CPU *current_cpu)
 ; Generate write.c
 
 (define (cgen-write.c)
-  (logit 1 "Generating " (gen-cpu-name) " write.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s write.c ...\n")
 
   (sim-analyze-insns!)
 
@@ -1033,7 +1033,7 @@ void
 ; Each instruction is implemented in its own function.
 
 (define (cgen-semantics.c)
-  (logit 1 "Generating " (gen-cpu-name) " semantics.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s semantics.c ...\n")
 
   (sim-analyze-insns!)
 
@@ -1082,7 +1082,7 @@ CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_" "attr)")
 ; This file consists of just the switch().  It is included by mainloop.c.
 
 (define (cgen-sem-switch.c)
-  (logit 1 "Generating " (gen-cpu-name) " sem-switch.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s sem-switch.c ...\n")
 
   (sim-analyze-insns!)
 
diff --git a/cgen/sim-decode.scm b/cgen/sim-decode.scm
index a4e620a..fb40b52 100644 (file)
--- a/cgen/sim-decode.scm
+++ b/cgen/sim-decode.scm
@@ -537,7 +537,7 @@ const IDESC *
 ; Entry point.  Generate decode.h.
 
 (define (cgen-decode.h)
-  (logit 1 "Generating " (gen-cpu-name) " decode.h ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s decode.h ...\n")
 
   (sim-analyze-insns!)
 
@@ -564,7 +564,7 @@ const IDESC *
 ; Entry point.  Generate decode.c.
 
 (define (cgen-decode.c)
-  (logit 1 "Generating " (gen-cpu-name) " decode.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s decode.c ...\n")
 
   (sim-analyze-insns!)
 
diff --git a/cgen/sim-model.scm b/cgen/sim-model.scm
index 53f528c..e5170f6 100644 (file)
--- a/cgen/sim-model.scm
+++ b/cgen/sim-model.scm
@@ -367,7 +367,7 @@ const MACH " (gen-sym mach) "_mach =
 ; Generate model.c
 
 (define (cgen-model.c)
-  (logit 1 "Generating " (gen-cpu-name) " model.c ...\n")
+  (logit 1 "Generating " (gen-cpu-name) "'s model.c ...\n")
 
   (sim-analyze-insns!)
 
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