arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE

We have two entries for ARM64_WORKAROUND_CLEAN_CACHE capability :

1) ARM Errata 826319, 827319, 824069, 819472 on A53 r0p[012]
2) ARM Errata 819472 on A53 r0p[01]

Both have the same work around. Merge these entries to avoid
duplicate entries for a single capability. Add a new Kconfig
entry to control the "capability" entry to make it easier
to handle combinations of the CONFIGs.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index bf57c48..6d2b25f 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -313,9 +313,13 @@ menu "Kernel Features"
 
 menu "ARM errata workarounds via the alternatives framework"
 
+config ARM64_WORKAROUND_CLEAN_CACHE
+       def_bool n
+
 config ARM64_ERRATUM_826319
        bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
        default y
+       select ARM64_WORKAROUND_CLEAN_CACHE
        help
          This option adds an alternative code sequence to work around ARM
          erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
@@ -337,6 +341,7 @@ config ARM64_ERRATUM_826319
 config ARM64_ERRATUM_827319
        bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
        default y
+       select ARM64_WORKAROUND_CLEAN_CACHE
        help
          This option adds an alternative code sequence to work around ARM
          erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
@@ -358,6 +363,7 @@ config ARM64_ERRATUM_827319
 config ARM64_ERRATUM_824069
        bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
        default y
+       select ARM64_WORKAROUND_CLEAN_CACHE
        help
          This option adds an alternative code sequence to work around ARM
          erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
@@ -380,6 +386,7 @@ config ARM64_ERRATUM_824069
 config ARM64_ERRATUM_819472
        bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
        default y
+       select ARM64_WORKAROUND_CLEAN_CACHE
        help
          This option adds an alternative code sequence to work around ARM
          erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 12f93e4..2e26375 100644 (file)
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -151,6 +151,7 @@ struct midr_range {
                .rv_max = MIDR_CPU_VAR_REV(v_max, r_max),       \
        }
 
+#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
 
 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 00d93a9..dc7ab05 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -570,24 +570,28 @@ static const struct midr_range arm64_harden_el2_vectors[] = {
 
 #endif
 
-const struct arm64_cpu_capabilities arm64_errata[] = {
+#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
+static const struct midr_range workaround_clean_cache[] = {
 #if    defined(CONFIG_ARM64_ERRATUM_826319) || \
        defined(CONFIG_ARM64_ERRATUM_827319) || \
        defined(CONFIG_ARM64_ERRATUM_824069)
-       {
-       /* Cortex-A53 r0p[012] */
-               .desc = "ARM errata 826319, 827319, 824069",
-               .capability = ARM64_WORKAROUND_CLEAN_CACHE,
-               ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
-               .cpu_enable = cpu_enable_cache_maint_trap,
-       },
+       /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
+       MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_819472
+       /* Cortex-A53 r0p[01] : ARM errata 819472 */
+       MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
 #endif
-#ifdef CONFIG_ARM64_ERRATUM_819472
+       {},
+};
+#endif
+
+const struct arm64_cpu_capabilities arm64_errata[] = {
+#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
        {
-       /* Cortex-A53 r0p[01] */
-               .desc = "ARM errata 819472",
+               .desc = "ARM errata 826319, 827319, 824069, 819472",
                .capability = ARM64_WORKAROUND_CLEAN_CACHE,
-               ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
+               ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
                .cpu_enable = cpu_enable_cache_maint_trap,
        },
 #endif