drm/amdgpu: add GMC support for ELM/BAF

V2: add golden_settings_baffin_a11 instead of reuse golden_settings_fiji_a10

Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 1e85b8f..cf1f668 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -43,6 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 
 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
+MODULE_FIRMWARE("amdgpu/baffin_mc.bin");
+MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin");
 
 static const u32 golden_settings_tonga_a11[] =
 {
@@ -73,6 +75,23 @@ static const u32 fiji_mgcg_cgcg_init[] =
        mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 };
 
+static const u32 golden_settings_baffin_a11[] =
+{
+       mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
+       mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
+       mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
+       mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
+};
+
+static const u32 golden_settings_ellesmere_a11[] =
+{
+       mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
+       mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
+       mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
+       mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
+       mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
+};
+
 static const u32 cz_mgcg_cgcg_init[] =
 {
        mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
@@ -103,6 +122,16 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
                                                 golden_settings_tonga_a11,
                                                 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
                break;
+       case CHIP_BAFFIN:
+               amdgpu_program_register_sequence(adev,
+                                                golden_settings_baffin_a11,
+                                                (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
+               break;
+       case CHIP_ELLESMERE:
+               amdgpu_program_register_sequence(adev,
+                                                golden_settings_ellesmere_a11,
+                                                (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
+               break;
        case CHIP_CARRIZO:
                amdgpu_program_register_sequence(adev,
                                                 cz_mgcg_cgcg_init,
@@ -209,6 +238,12 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
        case CHIP_TONGA:
                chip_name = "tonga";
                break;
+       case CHIP_BAFFIN:
+               chip_name = "baffin";
+               break;
+       case CHIP_ELLESMERE:
+               chip_name = "ellesmere";
+               break;
        case CHIP_FIJI:
        case CHIP_CARRIZO:
        case CHIP_STONEY: