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drm/nouveau/sec2: move interrupt handler to hw-specific module
authorBen Skeggs <bskeggs@redhat.com>
Tue, 14 Jan 2020 20:34:21 +0000 (06:34 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 15 Jan 2020 00:50:27 +0000 (10:50 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c

index f4cf682..bb79488 100644 (file)
 #include <subdev/top.h>
 
 static void
-nvkm_sec2_intr(struct nvkm_engine *engine)
-{
-       struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
-       struct nvkm_subdev *subdev = &sec2->engine.subdev;
-       struct nvkm_falcon *falcon = &sec2->falcon;
-       u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
-       u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
-
-       if (intr & 0x00000040) {
-               schedule_work(&sec2->work);
-               nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
-               intr &= ~0x00000040;
-       }
-
-       if (intr) {
-               nvkm_error(subdev, "unhandled intr %08x\n", intr);
-               nvkm_falcon_wr32(falcon, 0x004, intr);
-       }
-}
-
-static void
 nvkm_sec2_recv(struct work_struct *work)
 {
        struct nvkm_sec2 *sec2 = container_of(work, typeof(*sec2), work);
@@ -60,6 +39,13 @@ nvkm_sec2_recv(struct work_struct *work)
        nvkm_msgqueue_recv(sec2->queue);
 }
 
+static void
+nvkm_sec2_intr(struct nvkm_engine *engine)
+{
+       struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
+       sec2->func->intr(sec2);
+}
+
 static int
 nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
 {
index 75407cb..c6919f2 100644 (file)
@@ -26,6 +26,25 @@ static const struct nvkm_acr_lsf_func
 gp102_sec2_acr_0 = {
 };
 
+void
+gp102_sec2_intr(struct nvkm_sec2 *sec2)
+{
+       struct nvkm_subdev *subdev = &sec2->engine.subdev;
+       struct nvkm_falcon *falcon = &sec2->falcon;
+       u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
+       u32 intr = nvkm_falcon_rd32(falcon, 0x008) & disp & ~(disp >> 16);
+
+       if (intr & 0x00000040) {
+               schedule_work(&sec2->work);
+               nvkm_falcon_wr32(falcon, 0x004, 0x00000040);
+               intr &= ~0x00000040;
+       }
+
+       if (intr) {
+               nvkm_error(subdev, "unhandled intr %08x\n", intr);
+               nvkm_falcon_wr32(falcon, 0x004, intr);
+       }
+}
 
 static const struct nvkm_falcon_func
 gp102_sec2_flcn = {
@@ -44,6 +63,7 @@ gp102_sec2_flcn = {
 const struct nvkm_sec2_func
 gp102_sec2 = {
        .flcn = &gp102_sec2_flcn,
+       .intr = gp102_sec2_intr,
 };
 
 MODULE_FIRMWARE("nvidia/gp102/sec2/desc.bin");
index 6e28b96..e5ba6df 100644 (file)
@@ -5,8 +5,11 @@
 
 struct nvkm_sec2_func {
        const struct nvkm_falcon_func *flcn;
+       void (*intr)(struct nvkm_sec2 *);
 };
 
+void gp102_sec2_intr(struct nvkm_sec2 *);
+
 struct nvkm_sec2_fwif {
        int version;
        int (*load)(struct nvkm_sec2 *, int ver, const struct nvkm_sec2_fwif *);
index 5192b3a..e3eb08f 100644 (file)
@@ -38,6 +38,7 @@ tu102_sec2_flcn = {
 static const struct nvkm_sec2_func
 tu102_sec2 = {
        .flcn = &tu102_sec2_flcn,
+       .intr = gp102_sec2_intr,
 };
 
 static int