arm64/sysreg: Convert MVFR1_EL1 to automatic generation

Convert MVFR1_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-34-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 561968f..d4b787d 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,7 +170,6 @@
 #define SYS_ID_AFR0_EL1                        sys_reg(3, 0, 0, 1, 3)
 #define SYS_ID_MMFR5_EL1               sys_reg(3, 0, 0, 3, 6)
 
-#define SYS_MVFR1_EL1                  sys_reg(3, 0, 0, 3, 1)
 #define SYS_MVFR2_EL1                  sys_reg(3, 0, 0, 3, 2)
 
 #define SYS_ACTLR_EL1                  sys_reg(3, 0, 1, 0, 1)
@@ -692,15 +691,6 @@
 #define ID_DFR0_EL1_CopSDbg_SHIFT      4
 #define ID_DFR0_EL1_CopDbg_SHIFT       0
 
-#define MVFR1_EL1_SIMDFMAC_SHIFT       28
-#define MVFR1_EL1_FPHP_SHIFT           24
-#define MVFR1_EL1_SIMDHP_SHIFT 20
-#define MVFR1_EL1_SIMDSP_SHIFT 16
-#define MVFR1_EL1_SIMDInt_SHIFT        12
-#define MVFR1_EL1_SIMDLS_SHIFT 8
-#define MVFR1_EL1_FPDNaN_SHIFT 4
-#define MVFR1_EL1_FPFtZ_SHIFT  0
-
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN4_SHIFT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 7a56a9a..3ca7e61 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -645,6 +645,45 @@ Enum       3:0     SIMDReg
 EndEnum
 EndSysreg
 
+Sysreg MVFR1_EL1       3       0       0       3       1
+Res0   63:32
+Enum   31:28   SIMDFMAC
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   FPHP
+       0b0000  NI
+       0b0001  FPHP
+       0b0010  FPHP_CONV
+       0b0011  FP16
+EndEnum
+Enum   23:20   SIMDHP
+       0b0000  NI
+       0b0001  SIMDHP
+       0b0001  SIMDHP_FLOAT
+EndEnum
+Enum   19:16   SIMDSP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   SIMDInt
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    SIMDLS
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     FPDNaN
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     FPFtZ
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
 Sysreg ID_PFR2_EL1     3       0       0       3       4
 Res0   63:12
 Enum   11:8    RAS_frac