void Backend::notifyCycleBegin(unsigned Cycle) {
DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
for (HWEventListener *Listener : Listeners)
- Listener->onCycleBegin(Cycle);
+ Listener->onCycleBegin();
- DU->cycleEvent(Cycle);
- HWS->cycleEvent(Cycle);
+ DU->cycleEvent();
+ HWS->cycleEvent();
}
void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
void Backend::notifyCycleEnd(unsigned Cycle) {
DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
for (HWEventListener *Listener : Listeners)
- Listener->onCycleEnd(Cycle);
+ Listener->onCycleEnd();
}
} // namespace mca.
return RAT->collectWrites(Vec, RegID);
}
- void cycleEvent(unsigned Cycle) {
+ void cycleEvent() {
RCU->cycleEvent();
AvailableEntries =
CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
void onInstructionEvent(const HWInstructionEvent &Event) override;
- void onCycleBegin(unsigned Cycle) override { NumCycles++; }
+ void onCycleBegin() override { NumCycles++; }
- void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
+ void onCycleEnd() override { updateHistograms(); }
void onStallEvent(const HWStallEvent &Event) override;
class HWEventListener {
public:
// Generic events generated by the backend pipeline.
- virtual void onCycleBegin(unsigned Cycle) {}
- virtual void onCycleEnd(unsigned Cycle) {}
+ virtual void onCycleBegin() {}
+ virtual void onCycleEnd() {}
virtual void onInstructionEvent(const HWInstructionEvent &Event) {}
virtual void onStallEvent(const HWStallEvent &Event) {}
void onInstructionEvent(const HWInstructionEvent &Event) override;
- void onCycleBegin(unsigned Cycle) override { NumCycles++; }
+ void onCycleBegin() override { NumCycles++; }
- void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
+ void onCycleEnd() override { updateHistograms(); }
void printView(llvm::raw_ostream &OS) const override;
};
ReadyQueue[Idx] = &MCIS;
}
-void Scheduler::cycleEvent(unsigned /* unused */) {
+void Scheduler::cycleEvent() {
SmallVector<ResourceRef, 8> ResourcesFreed;
Resources->cycleEvent(ResourcesFreed);
bool canBeDispatched(unsigned Idx, const InstrDesc &Desc) const;
void scheduleInstruction(unsigned Idx, Instruction &MCIS);
- void cycleEvent(unsigned Cycle);
+ void cycleEvent();
#ifndef NDEBUG
void dump() const;
void onInstructionEvent(const HWInstructionEvent &Event) override;
- void onCycleBegin(unsigned Cycle) override { NumCycles++; }
+ void onCycleBegin() override { NumCycles++; }
- void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
+ void onCycleEnd() override { updateHistograms(); }
// Increases the number of used scheduler queue slots of every buffered
// resource in the Buffers set.
SummaryView(const SourceMgr &S, unsigned Width)
: Source(S), DispatchWidth(Width), TotalCycles(0) {}
- void onCycleEnd(unsigned /* unused */) override { ++TotalCycles; }
+ void onCycleEnd() override { ++TotalCycles; }
void printView(llvm::raw_ostream &OS) const override;
};
}
// Event handlers.
- void onCycleBegin(unsigned Cycle) override { CurrentCycle = Cycle; }
+ void onCycleEnd() override { ++CurrentCycle; }
void onInstructionEvent(const HWInstructionEvent &Event) override;
// print functionalities.