register_event(this, EVENT_FM7SUB_VSTART, 1.0 * 1000.0, false, &vstart_event_id);
register_event(this, EVENT_FM7SUB_DISPLAY_NMI, 20000.0, true, &nmi_event_id); // NEXT CYCLE_
for(i = 0; i < 8; i++) set_dpalette(i, i);
+ set_cyclesteal(config.dipswitch & 0x01); // CYCLE STEAL = bit0.
// subcpu->reset();
}
{
// BREAK + RESET
mainio->write_signal(FM7_MAINIO_PUSH_BREAK, 1, 1);
- event->register_event(mainio, EVENT_UP_BREAK, 2000.0 * 1000.0, false, NULL);
mainio->reset();
display->reset();
+ subcpu->reset();
+ maincpu->reset();
+ mainio->write_signal(FM7_MAINIO_PUSH_BREAK, 1, 1);
+ event->register_event(mainio, EVENT_UP_BREAK, 10000.0 * 1000.0, false, NULL);
}
void VM::run()
opn_cmdreg[i] = 0;
opn_address[i] = 0;
}
- printf("MAINIO: RESET\n");
+
// maincpu->reset();
}
case 0: // High inpedance
break;
case 1: // Read Data
+ opn[index]->write_io8(0, opn_address[index]);
+ opn_data[index] = opn[index]->read_io8(1);
break;
case 2: // Write Data
//printf("OPN %d WRITE DATA %02x to REG ADDR=%02x\n", index, val, opn_address[index]);