phy: qcom-qmp-ufs: drop start and pwrdn-ctrl abstraction

Drop the start and pwrdn-ctrl abstractions which are no longer needed
since the QMP driver split.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221012085002.24099-19-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 1a51f80..9b58d74 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -544,9 +544,6 @@ struct qmp_phy_cfg {
        /* array of registers with different offsets */
        const unsigned int *regs;
 
-       unsigned int start_ctrl;
-       unsigned int pwrdn_ctrl;
-
        /* true, if PCS block has no separate SW_RESET register */
        bool no_pcs_sw_reset;
 };
@@ -662,9 +659,6 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = {
 
        .regs                   = msm8996_ufsphy_regs_layout,
 
-       .start_ctrl             = SERDES_START,
-       .pwrdn_ctrl             = SW_PWRDN,
-
        .no_pcs_sw_reset        = true,
 };
 
@@ -685,9 +679,6 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = sdm845_ufsphy_regs_layout,
 
-       .start_ctrl             = SERDES_START,
-       .pwrdn_ctrl             = SW_PWRDN,
-
        .no_pcs_sw_reset        = true,
 };
 
@@ -708,9 +699,6 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = sm6115_ufsphy_regs_layout,
 
-       .start_ctrl             = SERDES_START,
-       .pwrdn_ctrl             = SW_PWRDN,
-
        .no_pcs_sw_reset        = true,
 };
 
@@ -730,9 +718,6 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
        .vreg_list              = qmp_phy_vreg_l,
        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = sm8150_ufsphy_regs_layout,
-
-       .start_ctrl             = SERDES_START,
-       .pwrdn_ctrl             = SW_PWRDN,
 };
 
 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
@@ -751,9 +736,6 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
        .vreg_list              = qmp_phy_vreg_l,
        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = sm8150_ufsphy_regs_layout,
-
-       .start_ctrl             = SERDES_START,
-       .pwrdn_ctrl             = SW_PWRDN,
 };
 
 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
@@ -772,9 +754,6 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
        .vreg_list              = qmp_phy_vreg_l,
        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
        .regs                   = sm8150_ufsphy_regs_layout,
-
-       .start_ctrl             = SERDES_START,
-       .pwrdn_ctrl             = SW_PWRDN,
 };
 
 static void qmp_ufs_configure_lane(void __iomem *base,
@@ -832,8 +811,7 @@ static int qmp_ufs_com_init(struct qmp_phy *qphy)
        if (ret)
                goto err_disable_regulators;
 
-       qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-                       cfg->pwrdn_ctrl);
+       qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
 
        return 0;
 
@@ -933,8 +911,9 @@ static int qmp_ufs_power_on(struct phy *phy)
        /* Pull PHY out of reset state */
        if (!cfg->no_pcs_sw_reset)
                qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-       /* start SerDes and Phy-Coding-Sublayer */
-       qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
+       /* start SerDes */
+       qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
 
        status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
        ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
@@ -956,12 +935,12 @@ static int qmp_ufs_power_off(struct phy *phy)
        if (!cfg->no_pcs_sw_reset)
                qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 
-       /* stop SerDes and Phy-Coding-Sublayer */
-       qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+       /* stop SerDes */
+       qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
 
        /* Put PHY into POWER DOWN state: active low */
        qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-                       cfg->pwrdn_ctrl);
+                       SW_PWRDN);
 
        return 0;
 }