arm64: dts: imx8m: add cache info

i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache.
 - Icache is 2-way set associative
 - Dcache is 4-way set associative
 - L2cache is 16-way set associative
 - Line size are 64bytes

Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache.

So add the cache info in device tree and let use could see that
from /sys/devices/system/cpu/cpu[x]/cache/

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index c2f3f11..5b9c2cc 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -65,6 +65,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MM_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        nvmem-cells = <&cpu_speed_grade>;
@@ -80,6 +86,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MM_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        cpu-idle-states = <&cpu_pd_wait>;
@@ -93,6 +105,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MM_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        cpu-idle-states = <&cpu_pd_wait>;
@@ -106,6 +124,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MM_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        cpu-idle-states = <&cpu_pd_wait>;
@@ -114,6 +138,10 @@
 
                A53_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
+                       cache-size = <0x80000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index da6c942..ba23b41 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -63,6 +63,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MN_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        nvmem-cells = <&cpu_speed_grade>;
@@ -78,6 +84,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MN_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        cpu-idle-states = <&cpu_pd_wait>;
@@ -91,6 +103,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MN_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        cpu-idle-states = <&cpu_pd_wait>;
@@ -104,6 +122,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MN_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        cpu-idle-states = <&cpu_pd_wait>;
@@ -112,6 +136,10 @@
 
                A53_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
+                       cache-size = <0x80000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 04d259d..9777837 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -51,6 +51,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
                };
@@ -62,6 +68,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
                };
@@ -73,6 +85,12 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
                };
@@ -84,12 +102,22 @@
                        clock-latency = <61036>;
                        clocks = <&clk IMX8MP_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        #cooling-cells = <2>;
                };
 
                A53_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
+                       cache-size = <0x80000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 972766b..95d8b95 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -102,6 +102,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
@@ -116,6 +122,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
@@ -128,6 +140,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
@@ -140,6 +158,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clk IMX8MQ_CLK_ARM>;
                        enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
                        #cooling-cells = <2>;
@@ -147,6 +171,10 @@
 
                A53_L2: l2-cache0 {
                        compatible = "cache";
+                       cache-level = <2>;
+                       cache-size = <0x100000>;
+                       cache-line-size = <64>;
+                       cache-sets = <1024>;
                };
        };