+2007-09-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR 658
+ * 386-dis.c (index64): New.
+ (index32): Likewise.
+ (intel_index64): Likewise.
+ (intel_index32): Likewise.
+ (att_index64): Likewise.
+ (att_index32): Likewise.
+ (print_insn): Set index64 and index32.
+ (OP_E_extended): Use index64/index32 for index register for
+ SIB with INDEX == 4.
+
+ * i386-opc.h (RegEiz): New.
+ (RegRiz): Likewise.
+
+ * i386-reg.tbl: Add eiz and riz.
+ * i386-tbl.h: Regenerated.
+
2007-09-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_extended): Always display scale for memory.
static const char **names8;
static const char **names8rex;
static const char **names_seg;
+static const char *index64;
+static const char *index32;
static const char **index16;
static const char *intel_names64[] = {
static const char *intel_names_seg[] = {
"es", "cs", "ss", "ds", "fs", "gs", "?", "?",
};
+static const char *intel_index64 = "riz";
+static const char *intel_index32 = "eiz";
static const char *intel_index16[] = {
"bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
};
static const char *att_names_seg[] = {
"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
};
+static const char *att_index64 = "%riz";
+static const char *att_index32 = "%eiz";
static const char *att_index16[] = {
"%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
};
names8 = intel_names8;
names8rex = intel_names8rex;
names_seg = intel_names_seg;
+ index64 = intel_index64;
+ index32 = intel_index32;
index16 = intel_index16;
open_char = '[';
close_char = ']';
names8 = att_names8;
names8rex = att_names8rex;
names_seg = att_names_seg;
+ index64 = att_index64;
+ index32 = att_index32;
index16 = att_index16;
open_char = '(';
close_char = ')';
havesib = 1;
FETCH_DATA (the_info, codep + 1);
index = (*codep >> 3) & 7;
- if (address_mode == mode_64bit || index != 0x4)
- /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */
- scale = (*codep >> 6) & 3;
+ scale = (*codep >> 6) & 3;
base = *codep & 7;
USED_REX (REX_X);
if (rex & REX_X)
? names64[base] : names32[base]);
if (havesib)
{
- if (haveindex)
+ /* ESP/RSP won't allow index. If base isn't ESP/RSP,
+ print index to tell base + index from base. */
+ if (scale != 0
+ || haveindex
+ || (havebase && base != ESP_REG_NUM))
{
if (!intel_syntax || havebase)
{
*obufp++ = separator_char;
*obufp = '\0';
}
- oappend (address_mode == mode_64bit
- && (sizeflag & AFLAG)
- ? names64[index] : names32[index]);
- }
- if (scale != 0 || haveindex)
- {
+ if (haveindex)
+ oappend (address_mode == mode_64bit
+ && (sizeflag & AFLAG)
+ ? names64[index] : names32[index]);
+ else
+ oappend (address_mode == mode_64bit
+ && (sizeflag & AFLAG)
+ ? index64 : index32);
+
*obufp++ = scale_char;
*obufp = '\0';
sprintf (scratchbuf, "%d", 1 << scale);
if (intel_syntax
&& (disp || modrm.mod != 0 || (base & 7) == 5))
{
- if ((bfd_signed_vma) disp >= 0)
+ if (!havedisp || (bfd_signed_vma) disp >= 0)
{
*obufp++ = '+';
*obufp = '\0';
disp = - (bfd_signed_vma) disp;
}
- print_displacement (scratchbuf, disp);
+ if (havedisp)
+ print_displacement (scratchbuf, disp);
+ else
+ print_operand_value (scratchbuf, 1, disp);
oappend (scratchbuf);
}
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
#define RegRip ((unsigned int ) ~0)
+/* EIZ and RIZ are fake index registers. */
+#define RegEiz (RegRip - 1)
+#define RegRiz (RegEiz - 1)
}
reg_entry;
// No type will make this register rejected for all purposes except
// for addressing. This saves creating one extra type for RIP.
rip, BaseIndex, 0, RegRip
+// No type will make these registers rejected for all purposes except
+// for addressing.
+eiz, BaseIndex, 0, RegEiz
+riz, BaseIndex, 0, RegRiz
// fp regs.
st(0), FloatReg|FloatAcc, 0, 0
st(1), FloatReg, 0, 1
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
0, RegRip },
+ { "eiz",
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 0, RegEiz },
+ { "riz",
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ 0, RegRiz },
{ "st(0)",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },