clk: mediatek: Fix corner case of tuner_en_reg

On MT8195, tuner_en_reg is moved to register offest 0x0.
If we only judge by tuner_en_reg, it may lead to wrong address.
Add tuner_en_bit to the check condition. And it has been confirmed,
on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
clock square control.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-4-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 7fb001a..99ada6e 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -332,7 +332,7 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
                pll->pcw_chg_addr = pll->base_addr + REG_CON1;
        if (data->tuner_reg)
                pll->tuner_addr = base + data->tuner_reg;
-       if (data->tuner_en_reg)
+       if (data->tuner_en_reg || data->tuner_en_bit)
                pll->tuner_en_addr = base + data->tuner_en_reg;
        if (data->en_reg)
                pll->en_addr = base + data->en_reg;