clk: meson: axg: spread spectrum is on mpll2

[ Upstream commit dc4e62d373f881cbf51513296a6db7806516a01a ]

After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.

Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 02229d0..4e7dac2 100644 (file)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -461,11 +461,6 @@ static struct clk_regmap axg_mpll0_div = {
                        .shift   = 16,
                        .width   = 9,
                },
-               .ssen = {
-                       .reg_off = HHI_MPLL_CNTL,
-                       .shift   = 25,
-                       .width   = 1,
-               },
                .misc = {
                        .reg_off = HHI_PLL_TOP_MISC,
                        .shift   = 0,
@@ -560,6 +555,11 @@ static struct clk_regmap axg_mpll2_div = {
                        .shift   = 16,
                        .width   = 9,
                },
+               .ssen = {
+                       .reg_off = HHI_MPLL_CNTL,
+                       .shift   = 25,
+                       .width   = 1,
+               },
                .misc = {
                        .reg_off = HHI_PLL_TOP_MISC,
                        .shift   = 2,