ARM: sunxi: dt: add PRCM clk and reset controller subdevices

Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset
controller subdevices.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 5e9f01a..90398fa 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -690,6 +690,44 @@
                prcm@01f01400 {
                        compatible = "allwinner,sun6i-a31-prcm";
                        reg = <0x01f01400 0x200>;
+
+                       ar100: ar100_clk {
+                               compatible = "allwinner,sun6i-a31-ar100-clk";
+                               #clock-cells = <0>;
+                               clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                               clock-output-names = "ar100";
+                       };
+
+                       ahb0: ahb0_clk {
+                               compatible = "fixed-factor-clock";
+                               #clock-cells = <0>;
+                               clock-div = <1>;
+                               clock-mult = <1>;
+                               clocks = <&ar100>;
+                               clock-output-names = "ahb0";
+                       };
+
+                       apb0: apb0_clk {
+                               compatible = "allwinner,sun6i-a31-apb0-clk";
+                               #clock-cells = <0>;
+                               clocks = <&ahb0>;
+                               clock-output-names = "apb0";
+                       };
+
+                       apb0_gates: apb0_gates_clk {
+                               compatible = "allwinner,sun6i-a31-apb0-gates-clk";
+                               #clock-cells = <1>;
+                               clocks = <&apb0>;
+                               clock-output-names = "apb0_pio", "apb0_ir",
+                                               "apb0_timer", "apb0_p2wi",
+                                               "apb0_uart", "apb0_1wire",
+                                               "apb0_i2c";
+                       };
+
+                       apb0_rst: apb0_rst {
+                               compatible = "allwinner,sun6i-a31-clock-reset";
+                               #reset-cells = <1>;
+                       };
                };
 
                cpucfg@01f01c00 {