pinctrl: sunxi: Support I/O bias voltage setting on H6

H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.

Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).

This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:

  commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")

Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
index ef4268c..3cc1121 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
        .irq_banks = 4,
        .irq_bank_map = h6_irq_bank_map,
        .irq_read_needs_mux = true,
+       .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 };
 
 static int h6_pinctrl_probe(struct platform_device *pdev)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 98c4de5..0cbca30 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
                                         unsigned pin,
                                         struct regulator *supply)
 {
+       unsigned short bank = pin / PINS_PER_BANK;
+       unsigned long flags;
        u32 val, reg;
        int uV;
 
@@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
                reg &= ~IO_BIAS_MASK;
                writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
                return 0;
+       case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
+               val = uV <= 1800000 ? 1 : 0;
+
+               raw_spin_lock_irqsave(&pctl->lock, flags);
+               reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
+               reg &= ~(1 << bank);
+               writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
+               raw_spin_unlock_irqrestore(&pctl->lock, flags);
+               return 0;
        default:
                return -EINVAL;
        }

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a62b813..44e30de 100644 (file)
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -95,6 +95,8 @@
 #define PINCTRL_SUN7I_A20      BIT(7)
 #define PINCTRL_SUN8I_R40      BIT(8)
 
+#define PIO_POW_MOD_SEL_REG    0x340
+
 enum sunxi_desc_bias_voltage {
        BIAS_VOLTAGE_NONE,
        /*
@@ -102,6 +104,11 @@ enum sunxi_desc_bias_voltage {
         * Pn_GRP_CONFIG registers, as seen on A80 SoC.
         */
        BIAS_VOLTAGE_GRP_CONFIG,
+       /*
+        * Bias voltage is set through PIO_POW_MOD_SEL_REG
+        * register, as seen on H6 SoC, for example.
+        */
+       BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 };
 
 struct sunxi_desc_function {