Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28944 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index da1de9a..659c2d7 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1076,10 +1076,11 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     break;
   }
   case ISD::OR:
-    if (SDNode *I = SelectBitfieldInsert(N)) {
-      Result = CodeGenMap[Op] = SDOperand(I, 0);
-      return;
-    }
+    if (N->getValueType(0) == MVT::i32)
+      if (SDNode *I = SelectBitfieldInsert(N)) {
+        Result = CodeGenMap[Op] = SDOperand(I, 0);
+        return;
+      }
       
     // Other cases are autogenerated.
     break;

diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index e43c0eb..46cc7d7 100644 (file)
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -134,8 +134,6 @@ def XORIS8  : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
                       "xoris $dst, $src1, $src2", IntGeneral,
                    [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
 
-
-                   
 def ADD8  : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
                      "add $rT, $rA, $rB", IntGeneral,
                      [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;