JIT imm12 encoding for constant pool entry references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index affec70..c103fab 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -181,6 +181,10 @@ namespace {
         // {11-0}  = imm12
         const MachineOperand &MO  = MI.getOperand(Op);
         const MachineOperand &MO1 = MI.getOperand(Op + 1);
+        if (!MO.isReg()) {
+          emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
+          return 0;
+        }
         unsigned Reg = getARMRegisterNumbering(MO.getReg());
         int32_t Imm12 = MO1.getImm();
         uint32_t Binary;