ARM: dts: NSP: Wire up switch interrupts

The Switch Register Access Block (SRAB) has one interrupt for link state
change on each ports (0-5, 7-8) a PHY interrupt, timestamping interrupt
and sleep timer interrupts for each management ports (5,7,8). Wire those
up so we can utilize them to speed up link resolution.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 09ba850..ec869a8 100644 (file)
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -377,7 +377,36 @@
 
                srab: srab@36000 {
                        compatible = "brcm,nsp-srab";
-                       reg = <0x36000 0x1000>;
+                       reg = <0x36000 0x1000>,
+                             <0x3f308 0x8>,
+                             <0x3f410 0xc>;
+                       reg-names = "srab", "mux_config", "sgmii";
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "link_state_p0",
+                                         "link_state_p1",
+                                         "link_state_p2",
+                                         "link_state_p3",
+                                         "link_state_p4",
+                                         "link_state_p5",
+                                         "link_state_p7",
+                                         "link_state_p8",
+                                         "phy",
+                                         "ts",
+                                         "imp_sleep_timer_p5",
+                                         "imp_sleep_timer_p7",
+                                         "imp_sleep_timer_p8";
                        #address-cells = <1>;
                        #size-cells = <0>;