Add support for the isLoad and isStore flags, needed by the instruction scheduler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 8551a55..82df28a 100644 (file)
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -71,6 +71,8 @@ namespace llvm {
     bool isBranch;
     bool isBarrier;
     bool isCall;
+    bool isLoad;
+    bool isStore;
     bool isTwoAddress;
     bool isTerminator;
     bool hasDelaySlot;

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index ba21405..f7225f0 100644 (file)
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -195,6 +195,8 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   isBranch     = R->getValueAsBit("isBranch");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
+  isLoad       = R->getValueAsBit("isLoad");
+  isStore      = R->getValueAsBit("isStore");
   isTwoAddress = R->getValueAsBit("isTwoAddress");
   isTerminator = R->getValueAsBit("isTerminator");
   hasDelaySlot = R->getValueAsBit("hasDelaySlot");

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index c02eda1..69570bc 100644 (file)
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -113,6 +113,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
   if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
   if (Inst.isCall)       OS << "|M_CALL_FLAG";
+  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
+  if (Inst.isStore)      OS << "|M_STORE_FLAG";
   if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
   if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
   OS << ", 0";