def: InstRW<[BWWriteResGroup7], (instregex "BLSR64rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "BZHI32rr")>;
def: InstRW<[BWWriteResGroup7], (instregex "BZHI64rr")>;
-def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[BWWriteResGroup7], (instregex "LEA(16|32|64)(_32)?r")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSBrr64")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSDrr64")>;
def: InstRW<[BWWriteResGroup7], (instregex "MMX_PABSWrr64")>;
def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
-def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1;
def: InstRW<[SKLWriteResGroup8], (instregex "BLSR64rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "BZHI32rr")>;
def: InstRW<[SKLWriteResGroup8], (instregex "BZHI64rr")>;
-def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SKLWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let Latency = 1;
def: InstRW<[SKXWriteResGroup8], (instregex "BLSR64rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "BZHI32rr")>;
def: InstRW<[SKXWriteResGroup8], (instregex "BZHI64rr")>;
-def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)r")>;
+def: InstRW<[SKXWriteResGroup8], (instregex "LEA(16|32|64)(_32)?r")>;
def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let Latency = 1;