drm/amd/display: Do a reg update instead of set when writing ODM color format

[why]
If a set is done, DSC settings are zeroed out, leading to no DSC for the modes
that require ODM, such as 8k60.

This was a regression introduced by 5a4f26295176bbfc776c75aaf0f6dd8ccf806958.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index d0b317e..26a66cc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -262,7 +262,7 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
        else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
                data_fmt = 2;
 
-       REG_SET(OPTC_DATA_FORMAT_CONTROL, 0, OPTC_DATA_FORMAT, data_fmt);
+       REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
 
        REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
                        OPTC_NUM_OF_INPUT_SEGMENT, 1,