fetch byte from name tbl, attr tbl, ptn tbl.

diff --git a/simulation/ppu/render.vhd b/simulation/ppu/render.vhd
index 8a7d465..bcf95b4 100644 (file)
--- a/simulation/ppu/render.vhd
+++ b/simulation/ppu/render.vhd
@@ -1,6 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.conv_std_logic_vector;
+use ieee.std_logic_unsigned.all;
 
 entity ppu_render is 
     port (  clk         : in std_logic;
@@ -71,6 +72,8 @@ constant HSCAN_MAX    : integer := 340;
 signal rst              : std_logic;
 signal clk_n            : std_logic;
 
+signal io_oe_n          : std_logic;
+
 signal render_en_n      : std_logic;
 signal render_x_res_n   : std_logic;
 signal render_y_en_n    : std_logic;
@@ -79,9 +82,15 @@ signal render_y_res_n   : std_logic;
 signal cur_x            : std_logic_vector(X_SIZE - 1 downto 0);
 signal cur_y            : std_logic_vector(X_SIZE - 1 downto 0);
 
-signal nt_oe_n          : std_logic;
 signal nt_we_n          : std_logic;
+signal attr_we_n        : std_logic;
+signal ptn_l_we_n       : std_logic;
+signal ptn_h_we_n       : std_logic;
+
 signal nt_val           : std_logic_vector (dsize - 1 downto 0);
+signal attr_val         : std_logic_vector (dsize - 1 downto 0);
+signal ptn_l_val        : std_logic_vector (dsize - 1 downto 0);
+signal ptn_h_val        : std_logic_vector (dsize - 1 downto 0);
 
 signal vram_addr        : std_logic_vector (asize - 1 downto 0);
 
@@ -103,9 +112,7 @@ begin
     ale <= cur_x(0) when rst_n = '1' else init_ale;
     rd_n <= cur_x(0) when rst_n = '1' else init_rd_n;
     wr_n <= '1' when rst_n = '1' else init_wr_n;
-
-    nt_we_n <= cur_x(0) when rst_n = '1' else '1';
-    nt_oe_n <= not cur_x(0) when rst_n = '1' else '1';
+    io_oe_n <= not cur_x(0) when rst_n = '1' else '1';
 
 
     -----fill test data during the reset.....
@@ -113,17 +120,23 @@ begin
         port map (clk, init_rd_n, init_wr_n, init_ale, vram_ad, vram_a);
 
 
+    --current x,y pos
     cur_x_inst : counter_register generic map (X_SIZE)
             port map (clk, render_x_res_n, render_en_n, cur_x);
-    --y pos increment when x pos reset.
     cur_y_inst : counter_register generic map (X_SIZE)
             port map (clk, render_y_res_n, render_y_en_n, cur_y);
 
-    name_t : d_flip_flop generic map(dsize)
+    nt_inst : d_flip_flop generic map(dsize)
             port map (clk_n, rst_n, '1', nt_we_n, vram_ad, nt_val);
+    at_inst : d_flip_flop generic map(dsize)
+            port map (clk_n, rst_n, '1', attr_we_n, vram_ad, attr_val);
+    ptn_l_inst : d_flip_flop generic map(dsize)
+            port map (clk_n, rst_n, '1', ptn_l_we_n, vram_ad, ptn_l_val);
+    ptn_h_inst : d_flip_flop generic map(dsize)
+            port map (clk_n, rst_n, '1', ptn_h_we_n, vram_ad, ptn_h_val);
 
     vram_io_buf : tri_state_buffer generic map (dsize)
-            port map (nt_oe_n, vram_addr(dsize - 1 downto 0), vram_ad);
+            port map (io_oe_n, vram_addr(dsize - 1 downto 0), vram_ad);
 
     vram_a_buf : tri_state_buffer generic map (6)
             port map (rst, vram_addr(asize - 1 downto dsize), vram_a);
@@ -133,8 +146,8 @@ begin
         if (rst_n = '0') then
             render_x_res_n <= '0';
             render_y_res_n <= '0';
+            nt_we_n <= '1';
         else
-
             if (clk'event) then
                 --x pos reset.
                 if (clk = '1' and 
@@ -166,15 +179,58 @@ begin
                 ----fetch name table byte.
                 if (cur_x (2 downto 0) = "000" ) then
                     --vram addr is incremented every 8 cycle.
-                    vram_addr(dsize - 1 downto 0) <= "000" & cur_x(7 downto 3);
+                    --name table at 0x2000
+                    vram_addr(dsize - 1 downto 0) 
+                        <= "000" & cur_x(dsize - 1 downto 3);
                     vram_addr(asize - 1 downto dsize) <= "100000";
+                end if;
+
+                if (cur_x (2 downto 0) = "001" ) then
+                    nt_we_n <= '0';
+                else
+                    nt_we_n <= '1';
+                end if;
 
                 ----fetch attr table byte.
-                elsif (cur_x (2 downto 0) = "010" ) then
+                if (cur_x (2 downto 0) = "010" ) then
                     --vram addr is incremented every 8 cycle.
-                    vram_addr(dsize - 1 downto 0) <= "110" & cur_x(7 downto 3);
+                    --attr table at 0x23c0
+                    vram_addr(dsize - 1 downto 0) 
+                        <= "110" & cur_x(dsize - 1 downto 3);
                     vram_addr(asize - 1 downto dsize) <= "100011";
-                end if;--if (cur_x (2 downto 0) = "000" ) then
+                end if;--if (cur_x (2 downto 0) = "010" ) then
+
+                if (cur_x (2 downto 0) = "011" ) then
+                    attr_we_n <= '0';
+                else
+                    attr_we_n <= '1';
+                end if;
+
+                ----fetch pattern table low byte.
+                if (cur_x (2 downto 0) = "100" ) then
+                    --vram addr is incremented every 8 cycle.
+                    vram_addr(dsize - 1 downto 0) <= nt_val;
+                    vram_addr(asize - 1 downto dsize) <= "000000";
+                end if;--if (cur_x (2 downto 0) = "100" ) then
+
+                if (cur_x (2 downto 0) = "101" ) then
+                    ptn_l_we_n <= '0';
+                else
+                    ptn_l_we_n <= '1';
+                end if;
+
+                ----fetch pattern table high byte.
+                if (cur_x (2 downto 0) = "110" ) then
+                    --vram addr is incremented every 8 cycle.
+                    vram_addr(dsize - 1 downto 0) <= nt_val + 1;
+                    vram_addr(asize - 1 downto dsize) <= "000000";
+                end if;
+
+                if (cur_x (2 downto 0) = "111" ) then
+                    ptn_h_we_n <= '0';
+                else
+                    ptn_h_we_n <= '1';
+                end if;--if (cur_x (2 downto 0) = "001" ) then
             end if; --if (clk'event and clk = '1') then
 
         end if;--if (rst_n = '0') then
@@ -239,7 +295,7 @@ begin
     p3 : process
     variable i : integer := 0;
     variable tmp : std_logic_vector (size8 - 1 downto 0);
-    constant loopcnt : integer := 20;
+    constant loopcnt : integer := 10;
     begin
 
         wait for 5 us;
@@ -256,6 +312,19 @@ begin
             v_ale <= '0';
             v_rd_n <= '1';
             v_wr_n <= '0';
+            v_addr(7 downto 0) <= conv_std_logic_vector(96 + 16 * i, size8);
+            wait for ppu_clk;
+
+            --write attr tbl #0
+            v_ale <= '1';
+            v_rd_n <= '1';
+            v_wr_n <= '1';
+            v_addr <= conv_std_logic_vector(16#23c0# + i, size14);
+            wait for ppu_clk;
+            v_addr(7 downto 0) <= (others => 'Z');
+            v_ale <= '0';
+            v_rd_n <= '1';
+            v_wr_n <= '0';
             v_addr(7 downto 0) <= conv_std_logic_vector(16#a0# + i, size8);
             wait for ppu_clk;
         end loop;