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arm64: dts: ls1028a: Fix incorrect I2C clock divider
authorChuanhua Han <chuanhua.han@nxp.com>
Tue, 6 Aug 2019 08:42:22 +0000 (16:42 +0800)
committerShawn Guo <shawnguo@kernel.org>
Mon, 19 Aug 2019 14:04:49 +0000 (16:04 +0200)
Ls1028a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.

Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

index 1e155b0..5c7a173 100644 (file)
                        #size-cells = <0>;
                        reg = <0x0 0x2000000 0x0 0x10000>;
                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2010000 0x0 0x10000>;
                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2020000 0x0 0x10000>;
                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2030000 0x0 0x10000>;
                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2040000 0x0 0x10000>;
                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2050000 0x0 0x10000>;
                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2060000 0x0 0x10000>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };
 
                        #size-cells = <0>;
                        reg = <0x0 0x2070000 0x0 0x10000>;
                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&clockgen 4 1>;
+                       clocks = <&clockgen 4 3>;
                        status = "disabled";
                };