return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
}
-/* Base types */
-static void bl_gen_nop(void **ptr)
+static void st_nm32_p(void **ptr, uint32_t insn)
{
- uint32_t *p = *ptr;
+ uint16_t *p = *ptr;
- stl_p(p, 0);
+ stw_p(p, insn >> 16);
+ p++;
+ stw_p(p, insn >> 0);
p++;
+
*ptr = p;
}
+/* Base types */
+static void bl_gen_nop(void **ptr)
+{
+ if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+ st_nm32_p(ptr, 0x8000c000);
+ } else {
+ uint32_t *p = *ptr;
+
+ stl_p(p, 0);
+ p++;
+ *ptr = p;
+ }
+}
+
static void bl_gen_r_type(void **ptr, uint8_t opcode,
bl_reg rs, bl_reg rt, bl_reg rd,
uint8_t shift, uint8_t funct)