i965/gen6 depth surface: calculate LOD being rendered to

(08ef1dd for gen6)

This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 0b1d097..96825c6 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -783,6 +783,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
    uint32_t surftype;
    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
    GLenum gl_target = params->depth.mt->target;
+   unsigned int lod;
 
    switch (gl_target) {
    case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -806,6 +807,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
                                    NULL,
                                    &tile_mask_x, &tile_mask_y);
 
+   lod = params->depth.level - params->depth.mt->first_level;
+
    /* 3DSTATE_DEPTH_BUFFER */
    {
       uint32_t tile_x = draw_x & tile_mask_x;

diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 8ee969f..9e03577 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -49,6 +49,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
    uint32_t surftype;
    unsigned int depth = 1;
    GLenum gl_target = GL_TEXTURE_2D;
+   unsigned int lod;
    const struct intel_renderbuffer *irb = NULL;
    const struct gl_renderbuffer *rb = NULL;
 
@@ -97,6 +98,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
       break;
    }
 
+   lod = irb ? irb->mt_level - irb->mt->first_level : 0;
+
    BEGIN_BATCH(7);
    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
    OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |