PCI: cadence: Add new *ops* for CPU addr fixup

Cadence driver uses "mem" memory resource to obtain the offset of
configuration space address region, memory space address region and
message space address region. The obtained offset is used to program
the Address Translation Unit (ATU). However certain platforms like TI's
J721E SoC require the absolute address to be programmed in the ATU and
not just the offset. Add new *ops* for CPU addr fixup for the platform
drivers to provide the correct address to be programmed in the ATU.

Link: https://lore.kernel.org/r/20200722110317.4744-9-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index f889914..6069a46 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -328,15 +328,14 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
 static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
 {
        struct cdns_pcie *pcie = &rc->pcie;
-       struct resource *mem_res = pcie->mem_res;
        struct resource *bus_range = rc->bus_range;
        struct resource *cfg_res = rc->cfg_res;
        struct device *dev = pcie->dev;
        struct device_node *np = dev->of_node;
        struct of_pci_range_parser parser;
+       u64 cpu_addr = cfg_res->start;
        struct of_pci_range range;
        u32 addr0, addr1, desc1;
-       u64 cpu_addr;
        int r, err;
 
        /*
@@ -349,7 +348,9 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
 
-       cpu_addr = cfg_res->start - mem_res->start;
+       if (pcie->ops->cpu_addr_fixup)
+               cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
+
        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
        addr1 = upper_32_bits(cpu_addr);
@@ -478,14 +479,6 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
        }
        rc->cfg_res = res;
 
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
-       if (!res) {
-               dev_err(dev, "missing \"mem\"\n");
-               return -EINVAL;
-       }
-
-       pcie->mem_res = res;
-
        ret = cdns_pcie_start_link(pcie);
        if (ret) {
                dev_err(dev, "Failed to start link\n");

diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index f5c6bf6..6f5f07b 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -13,6 +13,8 @@
 #include <linux/of_device.h>
 #include "pcie-cadence.h"
 
+#define CDNS_PLAT_CPU_TO_BUS_ADDR      0x0FFFFFFF
+
 /**
  * struct cdns_plat_pcie - private data for this PCIe platform driver
  * @pcie: Cadence PCIe controller
@@ -30,6 +32,15 @@ struct cdns_plat_pcie_of_data {
 
 static const struct of_device_id cdns_plat_pcie_of_match[];
 
+static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
+{
+       return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
+}
+
+static const struct cdns_pcie_ops cdns_plat_ops = {
+       .cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
+};
+
 static int cdns_plat_pcie_probe(struct platform_device *pdev)
 {
        const struct cdns_plat_pcie_of_data *data;
@@ -66,6 +77,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
 
                rc = pci_host_bridge_priv(bridge);
                rc->pcie.dev = dev;
+               rc->pcie.ops = &cdns_plat_ops;
                cdns_plat_pcie->pcie = &rc->pcie;
                cdns_plat_pcie->is_rc = is_rc;
 
@@ -93,6 +105,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
                        return -ENOMEM;
 
                ep->pcie.dev = dev;
+               ep->pcie.ops = &cdns_plat_ops;
                cdns_plat_pcie->pcie = &ep->pcie;
                cdns_plat_pcie->is_rc = is_rc;
 

diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
index cd795f6..8a02981 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence.c
+++ b/drivers/pci/controller/cadence/pcie-cadence.c
@@ -73,7 +73,9 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
 
        /* Set the CPU address */
-       cpu_addr -= pcie->mem_res->start;
+       if (pcie->ops->cpu_addr_fixup)
+               cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
+
        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
        addr1 = upper_32_bits(cpu_addr);
@@ -100,7 +102,9 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
        }
 
        /* Set the CPU address */
-       cpu_addr -= pcie->mem_res->start;
+       if (pcie->ops->cpu_addr_fixup)
+               cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
+
        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
        addr1 = upper_32_bits(cpu_addr);

diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 36c493f..7c804ac 100644 (file)
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -254,6 +254,7 @@ struct cdns_pcie_ops {
        int     (*start_link)(struct cdns_pcie *pcie);
        void    (*stop_link)(struct cdns_pcie *pcie);
        bool    (*link_up)(struct cdns_pcie *pcie);
+       u64     (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
 };
 
 /**