setOperationAction(ISD::FSINCOS, VT, Expand);
}
- // Lower this to FGETSIGNx86 plus an AND.
+ // Lower this to MOVMSK plus an AND.
setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
SDLoc dl(Op);
MVT VT = Op.getSimpleValueType();
- // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
- SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
- DAG.getConstant(1, dl, VT));
- return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
+ MVT OpVT = N0.getSimpleValueType();
+ assert((OpVT == MVT::f32 || OpVT == MVT::f64) &&
+ "Unexpected type for FGETSIGN");
+
+ // Lower ISD::FGETSIGN to (AND (X86ISD::MOVMSK ...) 1).
+ MVT VecVT = (OpVT == MVT::f32 ? MVT::v4f32 : MVT::v2f64);
+ SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, N0);
+ Res = DAG.getNode(X86ISD::MOVMSK, dl, MVT::i32, Res);
+ Res = DAG.getZExtOrTrunc(Res, dl, VT);
+ Res = DAG.getNode(ISD::AND, dl, VT, Res, DAG.getConstant(1, dl, VT));
+ return Res;
}
// Check whether an OR'd tree is PTEST-able.
case X86ISD::SETCC: return "X86ISD::SETCC";
case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
case X86ISD::FSETCC: return "X86ISD::FSETCC";
- case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
case X86ISD::CMOV: return "X86ISD::CMOV";
case X86ISD::BRCOND: return "X86ISD::BRCOND";
case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
/// 0s or 1s. Generally DTRT for C/C++ with NaNs.
FSETCC,
- /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
- /// result in an integer GPR. Needs masking for scalar result.
- FGETSIGNx86,
-
/// X86 conditional moves. Operand 0 and operand 1 are the two values
/// to select from. Operand 2 is the condition code, and operand 3 is the
/// flag operand produced by a CMP or TEST instruction. It also writes a
def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
-def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
SSEPackedSingle>, PS, VEX, VEX_L;
defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, v4f64, "movmskpd",
SSEPackedDouble>, PD, VEX, VEX_L;
-
- def : Pat<(i32 (X86fgetsign FR32:$src)),
- (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
- def : Pat<(i64 (X86fgetsign FR32:$src)),
- (SUBREG_TO_REG (i64 0),
- (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
- def : Pat<(i32 (X86fgetsign FR64:$src)),
- (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
- def : Pat<(i64 (X86fgetsign FR64:$src)),
- (SUBREG_TO_REG (i64 0),
- (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
}
defm MOVMSKPS : sse12_extr_sign_mask<VR128, v4f32, "movmskps",
defm MOVMSKPD : sse12_extr_sign_mask<VR128, v2f64, "movmskpd",
SSEPackedDouble>, PD;
-def : Pat<(i32 (X86fgetsign FR32:$src)),
- (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
- Requires<[UseSSE1]>;
-def : Pat<(i64 (X86fgetsign FR32:$src)),
- (SUBREG_TO_REG (i64 0),
- (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
- Requires<[UseSSE1]>;
-def : Pat<(i32 (X86fgetsign FR64:$src)),
- (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
- Requires<[UseSSE2]>;
-def : Pat<(i64 (X86fgetsign FR64:$src)),
- (SUBREG_TO_REG (i64 0),
- (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
- Requires<[UseSSE2]>;
-
//===---------------------------------------------------------------------===//
// SSE2 - Packed Integer Logical Instructions
//===---------------------------------------------------------------------===//