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target/arm: Fix offset for LD1R instructions
author
Richard Henderson
<richard.henderson@linaro.org>
Thu, 16 Aug 2018 13:05:27 +0000
(14:05 +0100)
committer
Peter Maydell
<peter.maydell@linaro.org>
Thu, 16 Aug 2018 13:05:27 +0000
(14:05 +0100)
The immediate should be scaled by the size of the memory reference,
not the size of the elements into which it is loaded.
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-sve.c
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diff --git
a/target/arm/translate-sve.c
b/target/arm/translate-sve.c
index
9e63b5f
..
f635822
100644
(file)
--- a/
target/arm/translate-sve.c
+++ b/
target/arm/translate-sve.c
@@
-4819,6
+4819,7
@@
static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
unsigned vsz = vec_full_reg_size(s);
unsigned psz = pred_full_reg_size(s);
unsigned esz = dtype_esz[a->dtype];
+ unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label();
TCGv_i64 temp;
@@
-4842,7
+4843,7
@@
static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
/* Load the data. */
temp = tcg_temp_new_i64();
- tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm <<
e
sz);
+ tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm <<
m
sz);
tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]);