bus: mhi: host: Optimize and update MMIO register write method

As of now, MMIO writes done after ready state transition use the
mhi_write_reg_field() API even though the whole register is being
written in most cases. Optimize this process by using mhi_write_reg()
API instead for those writes and use the mhi_write_reg_field()
API for MHI config registers only.

Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org>
Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/1650304226-11080-3-git-send-email-quic_jhugo@quicinc.com
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c
index 3842611..cbb86b2 100644 (file)
--- a/drivers/bus/mhi/host/init.c
+++ b/drivers/bus/mhi/host/init.c
@@ -439,74 +439,65 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
        struct device *dev = &mhi_cntrl->mhi_dev->dev;
        struct {
                u32 offset;
-               u32 mask;
                u32 val;
        } reg_info[] = {
                {
-                       CCABAP_HIGHER, U32_MAX,
+                       CCABAP_HIGHER,
                        upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
                },
                {
-                       CCABAP_LOWER, U32_MAX,
+                       CCABAP_LOWER,
                        lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr),
                },
                {
-                       ECABAP_HIGHER, U32_MAX,
+                       ECABAP_HIGHER,
                        upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
                },
                {
-                       ECABAP_LOWER, U32_MAX,
+                       ECABAP_LOWER,
                        lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr),
                },
                {
-                       CRCBAP_HIGHER, U32_MAX,
+                       CRCBAP_HIGHER,
                        upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
                },
                {
-                       CRCBAP_LOWER, U32_MAX,
+                       CRCBAP_LOWER,
                        lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr),
                },
                {
-                       MHICFG, MHICFG_NER_MASK,
-                       mhi_cntrl->total_ev_rings,
-               },
-               {
-                       MHICFG, MHICFG_NHWER_MASK,
-                       mhi_cntrl->hw_ev_rings,
-               },
-               {
-                       MHICTRLBASE_HIGHER, U32_MAX,
+                       MHICTRLBASE_HIGHER,
                        upper_32_bits(mhi_cntrl->iova_start),
                },
                {
-                       MHICTRLBASE_LOWER, U32_MAX,
+                       MHICTRLBASE_LOWER,
                        lower_32_bits(mhi_cntrl->iova_start),
                },
                {
-                       MHIDATABASE_HIGHER, U32_MAX,
+                       MHIDATABASE_HIGHER,
                        upper_32_bits(mhi_cntrl->iova_start),
                },
                {
-                       MHIDATABASE_LOWER, U32_MAX,
+                       MHIDATABASE_LOWER,
                        lower_32_bits(mhi_cntrl->iova_start),
                },
                {
-                       MHICTRLLIMIT_HIGHER, U32_MAX,
+                       MHICTRLLIMIT_HIGHER,
                        upper_32_bits(mhi_cntrl->iova_stop),
                },
                {
-                       MHICTRLLIMIT_LOWER, U32_MAX,
+                       MHICTRLLIMIT_LOWER,
                        lower_32_bits(mhi_cntrl->iova_stop),
                },
                {
-                       MHIDATALIMIT_HIGHER, U32_MAX,
+                       MHIDATALIMIT_HIGHER,
                        upper_32_bits(mhi_cntrl->iova_stop),
                },
                {
-                       MHIDATALIMIT_LOWER, U32_MAX,
+                       MHIDATALIMIT_LOWER,
                        lower_32_bits(mhi_cntrl->iova_stop),
                },
-               { 0, 0, 0 }
+               {0, 0}
        };
 
        dev_dbg(dev, "Initializing MHI registers\n");
@@ -547,13 +538,22 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
        mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER;
 
        /* Write to MMIO registers */
-       for (i = 0; reg_info[i].offset; i++) {
-               ret = mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset,
-                                         reg_info[i].mask, reg_info[i].val);
-               if (ret) {
-                       dev_err(dev, "Unable to write to MMIO registers\n");
-                       return ret;
-               }
+       for (i = 0; reg_info[i].offset; i++)
+               mhi_write_reg(mhi_cntrl, base, reg_info[i].offset,
+                             reg_info[i].val);
+
+       ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK,
+                                 mhi_cntrl->total_ev_rings);
+       if (ret) {
+               dev_err(dev, "Unable to write MHICFG register\n");
+               return ret;
+       }
+
+       ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK,
+                                 mhi_cntrl->hw_ev_rings);
+       if (ret) {
+               dev_err(dev, "Unable to write MHICFG register\n");
+               return ret;
        }
 
        return 0;