drm/i915: Remove redundant check for DG1

dg1_gt_workarounds_init() is only ever called for DG1, so there is no
point checking it again.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230306204954.753739-1-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cf05eec..4fa1400 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1512,16 +1512,12 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
                            L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 
        /* Wa_1409420604:dg1 */
-       if (IS_DG1(i915))
-               wa_mcr_write_or(wal,
-                               SUBSLICE_UNIT_LEVEL_CLKGATE2,
-                               CPSSUNIT_CLKGATE_DIS);
+       wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
+                       CPSSUNIT_CLKGATE_DIS);
 
        /* Wa_1408615072:dg1 */
        /* Empirical testing shows this register is unaffected by engine reset. */
-       if (IS_DG1(i915))
-               wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
-                           VSUNIT_CLKGATE_DIS_TGL);
+       wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
 }
 
 static void