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clk: rockchip: fix rk3188 hsadc_frac definition
author
Heiko Stübner
<heiko@sntech.de>
Thu, 30 Oct 2014 13:26:13 +0000
(14:26 +0100)
committer
Heiko Stuebner
<heiko@sntech.de>
Fri, 7 Nov 2014 22:41:14 +0000
(23:41 +0100)
The arguments to COMPOSITE_FRAC for hsadc_frac were mangled, leaving out the
the general clock flags argument. This results in strange effects, as only
sometimes a zero-division is reported as the wrong register is read.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3188.c
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diff --git
a/drivers/clk/rockchip/clk-rk3188.c
b/drivers/clk/rockchip/clk-rk3188.c
index
4dfd5e2
..
f88eb7d
100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3188.c
+++ b/
drivers/clk/rockchip/clk-rk3188.c
@@
-320,9
+320,9
@@
static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
- COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
+ COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
0,
RK2928_CLKSEL_CON(23), 0,
- RK2928_CLKGATE_CON(2), 7,
0,
GFLAGS),
+ RK2928_CLKGATE_CON(2), 7, GFLAGS),
MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),