List of clobbered registers fixed and added where it is lacking.
Signed-off-by: Nedeljko Babic <nbabic@mips.com>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
[fc_val_p] "=&f" (fc_val_p), [fc_val_m] "=&f" (fc_val_m),
[p_filter_coeffs_m] "+r" (p_filter_coeffs_m)
: [prec] "r" (prec)
+ : "memory"
);
}
out[n] = v;
[pole_coeffs] "r" (pole_coeffs)
: "$f0", "$f1", "$f2", "$f3", "$f4", "$f5",
"$f6", "$f7", "$f8", "$f9", "$f10", "$f11",
- "$f12", "$f13", "$f14", "$f15", "$f16"
+ "$f12", "$f13", "$f14", "$f15", "$f16", "memory"
);
}
#endif /* HAVE_INLINE_ASM */
: [weight_coeff_a] "f" (weight_coeff_a),
[weight_coeff_b] "f" (weight_coeff_b),
[length] "r" (length), [a_end]"r"(a_end)
- : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5"
+ : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "memory"
);
}
#endif /* HAVE_INLINE_ASM */
: [output]"=&f"(output)
: [fir_coef]"r"(fir_coef), [p_data]"r"(p_data)
- : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5"
+ : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "memory"
);
out[i] = output;
}
: [old_out0]"f"(old_out0), [old_out1]"f"(old_out1),
[old_out2]"f"(old_out2), [old_out3]"f"(old_out3),
[filter_coeffs]"r"(filter_coeffs)
- : "$f0", "$f1", "$f2", "$f3", "$f4"
+ : "$f0", "$f1", "$f2", "$f3", "$f4", "memory"
);
for (i = 5; i <= filter_length; i += 2) {
[old_out3]"+f"(old_out3),[p_filter_coeffs]"+r"(p_filter_coeffs),
[p_out]"+r"(p_out)
:
- : "$f4", "$f5"
+ : "$f4", "$f5", "memory"
);
FFSWAP(float, old_out0, old_out2);
}
: [fc_val]"=&f"(fc_val), [out_val]"+f"(out_val),
[out_val_i]"=&f"(out_val_i), [p_out]"+r"(p_out),
[p_filter_coeffs]"+r"(p_filter_coeffs)
+ :
+ : "memory"
);
}
out[n] = out_val;
[fc_val]"=&f"(fc_val), [p_filter_coeffs]"+r"(p_filter_coeffs),
[p_in]"+r"(p_in), [i]"+r"(i)
:
- : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7"
+ : "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "memory"
);
out[n+7] = sum_out8;
: [sum] "=&f" (sum), [a] "+r" (a), [b] "+r" (b)
: [a_end]"r"(a_end), [length] "r" (length)
- : "$f1", "$f2"
+ : "$f1", "$f2", "memory"
);
return sum;
}
[temp_reg5] "=&r" (temp_reg5), [temp_reg6] "=&r" (temp_reg6)
: [csa] "r" (csa), [ptr] "r" (ptr),
[MAX_lo] "r" (MAX_lo)
+ : "memory", "hi", "lo", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo",
+ "$ac3hi", "$ac3lo"
);
ptr += 18;
[out1] "=&f" (out1), [out2] "=&f" (out2),
[out3] "=&f" (out3), [out4] "=&f" (out4)
: [csa] "r" (csa), [ptr_end] "r" (ptr_end)
+ : "memory"
);
}
#define compute_antialias compute_antialias_mips_float
[tsin1]"+r"(tsin1), [tcos1]"+r"(tcos1),
[in1]"+r"(in1), [in2]"+r"(in2),
[in3]"+r"(in3), [in4]"+r"(in4)
+ :
+ : "memory"
);
z[j ].re = temp9;
: [z1]"r"(z1), [z2]"r"(z2),
[tsin1]"r"(tsin1), [tcos1]"r"(tcos1),
[tsin2]"r"(tsin2), [tcos2]"r"(tcos2)
+ : "memory"
);
z1[1].re = temp9;
[tmp]"=&f"(tmp), [f_j]"=&f"(f_j), [p_f]"+r"(p_f),
[j]"+r"(j), [p_fi]"+r"(p_fi)
: [i]"r"(i)
+ : "memory"
);
f[1] += val;
}
-/*
+ /*
* Copyright (c) 2012
* MIPS Technologies, Inc., California.
*
[sum1] "+r" (sum1), [w] "+r" (w), [temp3] "+r" (temp3)
: [p] "r" (p), [samples] "r" (samples), [min_asm] "r" (min_asm),
[max_asm] "r" (max_asm)
- : "hi","lo"
+ : "memory", "hi","lo"
);
samples += incr;
[w] "+r" (w), [w2] "+r" (w2), [samples] "+r" (samples),
[samples2] "+r" (samples2), [temp3] "+r" (temp3)
: [min_asm] "r" (min_asm), [max_asm] "r" (max_asm)
- : "hi", "lo"
+ : "memory", "hi", "lo", "$ac1hi", "$ac1lo"
);
samples += incr;
[w_asm2] "=&r" (w_asm2), [p_asm2] "=&r" (p_asm2), [sum1] "+r" (sum1)
: [w] "r" (w), [p] "r" (p), [samples] "r" (samples), [min_asm] "r" (min_asm),
[max_asm] "r" (max_asm)
- : "hi", "lo"
+ : "memory", "hi", "lo", "$ac1hi", "$ac1lo"
);
*dither_state= temp1;
: [in] "+r" (in), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3),
[t4] "=&r" (t4), [t5] "=&r" (t5), [t6] "=&r" (t6),
[t7] "=&r" (t7), [t8] "=&r" (t8)
+ :
+ : "memory"
);
for(j = 0; j < 2; j++) {
: [C_2] "r" (C_2), [in1] "r" (in1), [tmp1] "r" (tmp1), [C_8] "r" (C_8),
[C_4] "r" (C_4), [C_3] "r" (C_3), [C_1] "r" (C_1), [C_7] "r" (C_7),
[C_3A] "r" (C_3A), [C_5] "r" (C_5)
- : "hi", "lo"
+ : "memory", "hi", "lo", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo",
+ "$ac3hi", "$ac3lo"
);
}
[temp_reg5] "=&r" (temp_reg5), [temp_reg6] "=&r" (temp_reg6),
[out] "+r" (out)
: [tmp] "r" (tmp), [win] "r" (win), [buf] "r" (buf)
- : "hi", "lo"
+ : "memory", "hi", "lo", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo",
+ "$ac3hi", "$ac3lo"
);
}
[t_sample] "=&r" (t_sample)
: [synth_buf] "r" (synth_buf), [window] "r" (window),
[dither_state] "r" (dither_state), [incr1] "r" (incr1)
+ : "memory"
);
}
[val16] "=f" (val16), [val23] "=f" (val23),
[val24] "=f" (val24), [val31] "=f" (val31)
: [tab] "r" (tab)
+ : "memory"
);
__asm__ volatile (
[val19] "=f" (val19), [val20] "=f" (val20),
[val27] "=f" (val27), [val28] "=f" (val28)
: [tab] "r" (tab)
+ : "memory"
);
__asm__ volatile (
[val17] "=f" (val17), [val22] "=f" (val22),
[val25] "=f" (val25), [val30] "=f" (val30)
: [tab] "r" (tab)
+ : "memory"
);
__asm__ volatile (
[val18] "=f" (val18), [val21] "=f" (val21),
[val26] "=f" (val26), [val29] "=f" (val29)
: [tab] "r" (tab)
+ : "memory"
);
__asm__ volatile (
[out3] "=&f" (out3), [out4] "=&f" (out4),
[out5] "=&f" (out5)
: [in] "r" (in)
+ : "memory"
);
/* loop 3 */
[c7] "=&f" (c7), [c8] "=&f" (c8),
[c9] "=&f" (c9)
: [in] "r" (in), [tmp] "r" (tmp)
+ : "memory"
);
/* loop 4 */
[s2] "=&f" (s2), [s3] "=&f" (s3)
: [tmp] "r" (tmp), [win] "r" (win),
[buf] "r" (buf), [out] "r" (out)
+ : "memory"
);
}